215 lines
7.9 KiB
Verilog
215 lines
7.9 KiB
Verilog
// femtorv32, a minimalistic RISC-V RV32I core
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// (minus SYSTEM and FENCE that are not implemented)
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//
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// Bruno Levy, 2020-2021
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//
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// This file: FGA: Femto Graphics Adapter
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// Note: VRAM is write-only ! (the read port is used by HDMI)
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// Mode 1: 320x200x16bpp.
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`include "HDMI_clock.v"
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`include "TMDS_encoder.v"
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module FGA(
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input wire clk, // system clock
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input wire sel, // if zero, writes are ignored
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input wire [3:0] mem_wmask, // mem write mask and strobe /write Legal values are 000,0001,0010,0100,1000,0011,1100,1111
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input wire [16:0] mem_address, // address in graphic memory (128K), word-aligned
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input wire [31:0] mem_wdata, // data to be written
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input wire pixel_clk, // 25 MHz
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output wire [3:0] gpdi_dp, // HDMI signals, blue, green, red, clock
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// dgpi_dn generated by pins (see ulx3s.lpf)
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input wire io_wstrb,
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input wire io_rstrb,
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input wire sel_cntl, // select control register (R/W)
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input wire sel_dat, // select data in (W)
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output wire [31:0] rdata // data read from register
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);
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wire [14:0] vram_word_address = mem_address[16:2];
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reg [31:0] VRAM[32767:0];
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/************************* HDMI signal generation ***************************/
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// This part is just like a VGA generator.
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reg [9:0] X, Y; // current pixel coordinates
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reg hSync, vSync; // horizontal and vertical synchronization
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reg DrawArea; // asserted if current pixel is in drawing area
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reg mem_busy; // asserted if memory transfer is running.
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// read control register
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assign rdata = (io_rstrb && sel_cntl) ?
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{vSync,hSync,DrawArea,mem_busy,4'b0,2'b0,X,2'b0,Y} :
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32'b0;
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always @(posedge pixel_clk) begin
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DrawArea <= (X<640) && (Y<480);
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X <= (X==799) ? 0 : X+1;
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if(X==799) Y <= (Y==524) ? 0 : Y+1;
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hSync <= (X>=656) && (X<752);
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vSync <= (Y>=490) && (Y<492);
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end
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// Fetch pixel data
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reg [16:0] pix_address;
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reg [16:0] row_start;
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reg [15:0] pix_data;
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always @(posedge pixel_clk) begin
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if(X == 0) begin
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if(Y == 0) begin
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row_start <= 0;
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pix_address <= 0;
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end else begin
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// Increment row address every 2 Y (2 because 320x200->640x400)
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if(Y[0]) begin
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row_start <= row_start + 640;
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pix_address <= row_start + 640;
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end else begin
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pix_address <= row_start;
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end
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end
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end
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// Increment pix_address every 4 X (2 because 320x200->640x400 and 2 because 16 bpp)
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if(X[1:0] == 2'b11) pix_address <= pix_address + 4;
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// Draw 640x400 zone, and hide first pixel row (fetch delay)
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// Select word's 16msb or 16lsbs based on X[1] (again, every 4 X)
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pix_data <= (X == 0 || Y > 400) ? 0 :
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X[1] ? VRAM[pix_address[16:2]][31:16] : VRAM[pix_address[16:2]][15:0];
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end
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// Decode pixel data: RRRRR GGGGG 0 BBBBB
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wire [7:0] R = {pix_data[15:11],3'b000};
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wire [7:0] G = {pix_data[10:5], 2'b00 };
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wire [7:0] B = {pix_data[4:0], 3'b000};
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// RGB TMDS encoding
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// Generate 10-bits TMDS red,green,blue signals. Blue embeds HSync/VSync in its
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// control part.
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wire [9:0] TMDS_R, TMDS_G, TMDS_B;
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TMDS_encoder encode_R(.clk(pixel_clk), .VD(R), .CD(2'b00) , .VDE(DrawArea), .TMDS(TMDS_R));
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TMDS_encoder encode_G(.clk(pixel_clk), .VD(G), .CD(2'b00) , .VDE(DrawArea), .TMDS(TMDS_G));
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TMDS_encoder encode_B(.clk(pixel_clk), .VD(B), .CD({vSync,hSync}), .VDE(DrawArea), .TMDS(TMDS_B));
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// 250 MHz clock
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// This one needs some FPGA-specific specialized blocks (a PLL).
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wire clk_TMDS; // The 250 MHz clock used by the serializers.
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HDMI_clock hdmi_clock(.clk(pixel_clk), .hdmi_clk(clk_TMDS));
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// Modulo-10 clock divider (my version, using a 1-hot in a 10 bits ring)
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reg [9:0] TMDS_mod10=1;
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wire TMDS_shift_load = TMDS_mod10[9];
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always @(posedge clk_TMDS) TMDS_mod10 <= {TMDS_mod10[8:0],TMDS_mod10[9]};
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// Shifters
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// Every 10 clocks, we get a fresh R,G,B triplet from the TMDS encoders,
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// else we shift.
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reg [9:0] TMDS_shift_R=0, TMDS_shift_G=0, TMDS_shift_B=0;
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always @(posedge clk_TMDS) begin
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TMDS_shift_R <= TMDS_shift_load ? TMDS_R : {1'b0,TMDS_shift_R[9:1]};
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TMDS_shift_G <= TMDS_shift_load ? TMDS_G : {1'b0,TMDS_shift_G[9:1]};
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TMDS_shift_B <= TMDS_shift_load ? TMDS_B : {1'b0,TMDS_shift_B[9:1]};
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end
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// HDMI signal, positive part of the differential pairs
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// (negative part generated by the pins, see ulx3s.lpf)
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assign gpdi_dp[2] = TMDS_shift_R[0];
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assign gpdi_dp[1] = TMDS_shift_G[0];
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assign gpdi_dp[0] = TMDS_shift_B[0];
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assign gpdi_dp[3] = pixel_clk;
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/*************************************************************************/
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// control register - commands
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localparam SET_MODE = 7'd0; // TODO
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localparam SET_PALETTE_R = 7'd1; // TODO
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localparam SET_PALETTE_G = 7'd2; // TODO
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localparam SET_PALETTE_B = 7'd3; // TODO
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localparam SET_WWINDOW_X = 7'd4;
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localparam SET_WWINDOW_Y = 7'd5;
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// Emulation of SSD1351 OLED display.
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// - write window command, two commands:
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// (send 32 bits to IO_FGA_CNTL hardware register)
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// CMD=4: SET_WWINDOW_X: X2[11:0] X1[11:0] CMD[7:0]
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// CMD=5: SET_WWINDOW_Y: Y2[11:0] Y1[11:0] CMD[7:0]
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//
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// - write data: send 8 bits to IO_FGA_DAT hardware register
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// MSB first, encoding follows SSD1351: RRRRR GGGGG 0 BBBBB
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reg[9:0] window_x1, window_x2, window_y1, window_y2, window_x, window_y;
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reg[16:0] window_row_start;
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reg[16:0] window_byte_address;
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always @(posedge clk) begin
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if(io_wstrb) begin
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if(sel_cntl) begin
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case(mem_wdata[7:0])
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SET_WWINDOW_X: begin // SET_WWINDOW_X command
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window_x1 <= mem_wdata[19:8];
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window_x2 <= mem_wdata[31:20];
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window_x <= mem_wdata[19:8];
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mem_busy <= 1'b1;
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end
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SET_WWINDOW_Y: begin // SET_WWINDOW_Y command
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window_y1 <= mem_wdata[19:8];
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window_y2 <= mem_wdata[31:20];
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window_y <= mem_wdata[19:8];
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mem_busy <= 1'b1;
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window_row_start <= (mem_wdata[19:8] * 320 + window_x1) << 1;
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window_byte_address <= (mem_wdata[19:8] * 320 + window_x1) << 1;
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end
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endcase
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end else if(sel_dat) begin // one byte of data sent to IO_FGA_DAT
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// increment pixel address.
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window_byte_address <= window_byte_address + 1;
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if(window_byte_address[0]) begin
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if(window_x == window_x2) begin
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if(window_y == window_y2) begin
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mem_busy <= 1'b0;
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end else begin
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window_y <= window_y+1;
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window_x <= window_x1;
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window_byte_address <= window_row_start + 640;
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window_row_start <= window_row_start + 640;
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end
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end else begin
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window_x <= window_x + 1;
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end
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end
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end // if (sel_dat)
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end // if (wstrb)
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end // always @ (posedge clk)
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// write VRAM (interface with processor)
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always @(posedge clk) begin
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if(io_wstrb) begin
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if(sel_dat && mem_busy) begin // one byte of data sent to IO_FGA_DAT
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// write data to VRAM.
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case(window_byte_address[1:0])
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// Note: bytes are swapped (following SSD1351 norm)
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2'b00: VRAM[window_byte_address[16:2]][15:8 ] <= mem_wdata[7:0];
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2'b01: VRAM[window_byte_address[16:2]][ 0:7 ] <= mem_wdata[7:0];
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2'b10: VRAM[window_byte_address[16:2]][31:24] <= mem_wdata[7:0];
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2'b11: VRAM[window_byte_address[16:2]][23:16] <= mem_wdata[7:0];
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endcase
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end
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end else if(sel && !mem_busy) begin
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if(mem_wmask[0]) VRAM[vram_word_address][ 7:0 ] <= mem_wdata[ 7:0 ];
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if(mem_wmask[1]) VRAM[vram_word_address][15:8 ] <= mem_wdata[15:8 ];
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if(mem_wmask[2]) VRAM[vram_word_address][23:16] <= mem_wdata[23:16];
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if(mem_wmask[3]) VRAM[vram_word_address][31:24] <= mem_wdata[31:24];
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end
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end
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endmodule
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