34 lines
1.3 KiB
Plaintext
34 lines
1.3 KiB
Plaintext
// This file is part of www.nand2tetris.org
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// and the book "The Elements of Computing Systems"
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// by Nisan and Schocken, MIT Press.
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// File name: projects/03/b/RAM4K.hdl
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/**
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* Memory of 4K registers, each 16 bit-wide. Out holds the value
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* stored at the memory location specified by address. If load==1, then
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* the in value is loaded into the memory location specified by address
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* (the loaded value will be emitted to out from the next time step onward).
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*/
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CHIP RAM4K {
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IN in[16], load, address[12];
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OUT out[16];
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PARTS:
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DMux8Way(in=load, sel=address[9..11],
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a=ld0, b=ld1, c=ld2, d=ld3,
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e=ld4, f=ld5, g=ld6, h=ld7);
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RAM512(in=in, out=out0, load=ld0, address=address[0..8]);
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RAM512(in=in, out=out1, load=ld1, address=address[0..8]);
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RAM512(in=in, out=out2, load=ld2, address=address[0..8]);
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RAM512(in=in, out=out3, load=ld3, address=address[0..8]);
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RAM512(in=in, out=out4, load=ld4, address=address[0..8]);
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RAM512(in=in, out=out5, load=ld5, address=address[0..8]);
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RAM512(in=in, out=out6, load=ld6, address=address[0..8]);
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RAM512(in=in, out=out7, load=ld7, address=address[0..8]);
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Mux8Way16(a=out0, b=out1, c=out2, d=out3,
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e=out4, f=out5, g=out6, h=out7,
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sel=address[9..11], out=out);
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} |