salfter/nand2tetris_verilog

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salfter 727189c037 bit: timing's a bit wonky

2024-06-17 10:11:07 -07:00

.gitignore

initial commit: implement a NAND gate, and test it

2024-06-12 22:01:00 -07:00

add16_tb.v

16-bit adder

2024-06-13 21:13:15 -07:00

add16.v

16-bit adder

2024-06-13 21:13:15 -07:00

alu_tb.v

Update alu_tb.v

2024-06-14 13:55:39 -07:00

alu.v

ALU

2024-06-14 08:04:43 -07:00

and16_tb.v

and16 and or16

2024-06-13 14:12:48 -07:00

and16.v

and16 and or16

2024-06-13 14:12:48 -07:00

and_tb.v

Mux added, and some cleanup

2024-06-13 13:03:38 -07:00

and.v

fix module declarations

2024-06-13 13:29:36 -07:00

bit_tb.v

bit: timing's a bit wonky

2024-06-17 10:11:07 -07:00

bit.v

bit: timing's a bit wonky

2024-06-17 10:11:07 -07:00

dff_tb.v

dff: switch to Verilog primitives to get edge triggering

2024-06-14 16:13:09 -07:00

dff.v

dff: switch to Verilog primitives to get edge triggering

2024-06-14 16:13:09 -07:00

dmux4way_tb.v

1-to-4 demux

2024-06-13 18:55:53 -07:00

dmux4way.v

1-to-4 demux

2024-06-13 18:55:53 -07:00

dmux8way_tb.v

1-to-8 demux

2024-06-13 19:00:21 -07:00

dmux8way.v

1-to-8 demux

2024-06-13 19:00:21 -07:00

dmux_tb.v

Demux

2024-06-13 13:50:03 -07:00

dmux.v

1-to-4 demux

2024-06-13 18:55:53 -07:00

fulladder_tb.v

half and full adders

2024-06-13 19:58:39 -07:00

fulladder.v

half and full adders

2024-06-13 19:58:39 -07:00

halfadder_tb.v

half and full adders

2024-06-13 19:58:39 -07:00

halfadder.v

half and full adders

2024-06-13 19:58:39 -07:00

inc16_tb.v

16-bit increment

2024-06-13 21:19:30 -07:00

inc16.v

16-bit increment

2024-06-13 21:19:30 -07:00

Makefile

bit: timing's a bit wonky

2024-06-17 10:11:07 -07:00

mux4way16_tb.v

16-bit 4-to-1 mux

2024-06-13 18:21:15 -07:00

mux4way16.v

16-bit 4-to-1 mux

2024-06-13 18:21:15 -07:00

mux4way_tb.v

4-to-1 mux

2024-06-13 15:29:23 -07:00

mux4way.v

4-to-1 mux

2024-06-13 15:29:23 -07:00

mux8way16_tb.v

16-bit 8-to-1 mux

2024-06-13 18:28:20 -07:00

mux8way16.v

16-bit 8-to-1 mux

2024-06-13 18:28:20 -07:00

mux8way_tb.v

8-to-1 mux

2024-06-13 17:52:12 -07:00

mux8way.v

8-to-1 mux

2024-06-13 17:52:12 -07:00

mux16_tb.v

mux16

2024-06-13 14:23:05 -07:00

mux16.v

mux16

2024-06-13 14:23:05 -07:00

mux_tb.v

Mux added, and some cleanup

2024-06-13 13:03:38 -07:00

mux.v

fix module declarations

2024-06-13 13:29:36 -07:00

nand_tb.v

Mux added, and some cleanup

2024-06-13 13:03:38 -07:00

nand.v

fix module declarations

2024-06-13 13:29:36 -07:00

nor_tb.v

Mux added, and some cleanup

2024-06-13 13:03:38 -07:00

nor.v

fix module declarations

2024-06-13 13:29:36 -07:00

not16_tb.v

16-bit NOT

2024-06-13 13:24:54 -07:00

not16.v

16-bit NOT

2024-06-13 13:24:54 -07:00

not_tb.v

Mux added, and some cleanup

2024-06-13 13:03:38 -07:00

not.v

fix module declarations

2024-06-13 13:29:36 -07:00

or8way_tb.v

8-input OR

2024-06-13 14:43:34 -07:00

or8way.v

8-input OR

2024-06-13 14:43:34 -07:00

or16_tb.v

and16 and or16

2024-06-13 14:12:48 -07:00

or16.v

and16 and or16

2024-06-13 14:12:48 -07:00

or_tb.v

Mux added, and some cleanup

2024-06-13 13:03:38 -07:00

or.v

fix module declarations

2024-06-13 13:29:36 -07:00

README.md

initial commit: implement a NAND gate, and test it

2024-06-12 22:01:00 -07:00

xor_tb.v

Mux added, and some cleanup

2024-06-13 13:03:38 -07:00

xor.v

fix module declarations

2024-06-13 13:29:36 -07:00

README.md

nand2tetris_verilog

My attempt at learning Verilog by using it to implement the From Nand to Tetris design. Initial stages need Icarus Verilog, GTKWave, and make to test.