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tooling holes added, sent out for manufacturing

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This commit is contained in:
Scott Alfter
2023-07-28 22:23:39 -07:00
parent 18717d8266
commit aac1104c6e
21 changed files with 33841 additions and 14276 deletions
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3
.gitmodules vendored
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@@ -1,3 +1,6 @@
[submodule "firmware/ch32v003fun"]
path = firmware/ch32v003fun
url = https://github.com/cnlohr/ch32v003fun
[submodule "nixitest1/kicad-libs"]
path = nixitest1/kicad-libs
url = https://gitlab.com/salfter/kicad-libs

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%MOMM*%
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G04 Aperture macros list*
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0 Rectangle with rounded corners*
0 $1 Rounding radius*
0 $2 $3 $4 $5 $6 $7 $8 $9 X,Y pos of 4 corners*
0 Add a 4 corners polygon primitive as box body*
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0 Add four circle primitives for the rounded corners*
1,1,$1+$1,$2,$3*
1,1,$1+$1,$4,$5*
1,1,$1+$1,$6,$7*
1,1,$1+$1,$8,$9*
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20,1,$1+$1,$2,$3,$4,$5,0*
20,1,$1+$1,$4,$5,$6,$7,0*
20,1,$1+$1,$6,$7,$8,$9,0*
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G04 Aperture macros list end*
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M02*

2272
nixitest1/fabrication/nixitest1-F_Silkscreen.gbr Normal file
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File diff suppressed because it is too large Load Diff

1622
nixitest1/fabrication/nixitest1-NPTH-drl_map.gbr Normal file
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File diff suppressed because it is too large Load Diff

23
nixitest1/fabrication/nixitest1-NPTH.drl Normal file
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@@ -0,0 +1,23 @@
M48
; DRILL file {KiCad 7.0.6} date Fri 28 Jul 2023 09:33:29 PM PDT
; FORMAT={-:-/ absolute / metric / decimal}
; #@! TF.CreationDate,2023-07-28T21:33:29-07:00
; #@! TF.GenerationSoftware,Kicad,Pcbnew,7.0.6
; #@! TF.FileFunction,NonPlated,1,2,NPTH
FMAT,2
METRIC
; #@! TA.AperFunction,NonPlated,NPTH,ComponentDrill
T1C1.152
; #@! TA.AperFunction,NonPlated,NPTH,ComponentDrill
T2C3.500
%
G90
G05
T1
X81.286Y-60.234
X99.066Y-59.98
X99.574Y-92.746
T2
X89.85Y-80.02
T0
M30

4480
nixitest1/fabrication/nixitest1-PTH-drl_map.gbr Normal file
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File diff suppressed because it is too large Load Diff

184
nixitest1/fabrication/nixitest1-PTH.drl Normal file
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@@ -0,0 +1,184 @@
M48
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; FORMAT={-:-/ absolute / metric / decimal}
; #@! TF.CreationDate,2023-07-28T21:33:29-07:00
; #@! TF.GenerationSoftware,Kicad,Pcbnew,7.0.6
; #@! TF.FileFunction,Plated,1,2,PTH
FMAT,2
METRIC
; #@! TA.AperFunction,Plated,PTH,ViaDrill
T1C0.250
; #@! TA.AperFunction,Plated,PTH,ComponentDrill
T2C0.800
; #@! TA.AperFunction,Plated,PTH,ComponentDrill
T3C0.900
; #@! TA.AperFunction,Plated,PTH,ComponentDrill
T4C0.980
; #@! TA.AperFunction,Plated,PTH,ComponentDrill
T5C0.990
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T6C1.000
%
G90
G05
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X90.0Y-71.0
X90.0Y-89.0
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X94.0Y-88.0
X95.75Y-75.5
X95.75Y-80.0
X95.75Y-84.5
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T0
M30

127
nixitest1/fabrication/nixitest1-job.gbrjob Normal file
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@@ -0,0 +1,127 @@
{
"Header": {
"GenerationSoftware": {
"Vendor": "KiCad",
"Application": "Pcbnew",
"Version": "7.0.6"
},
"CreationDate": "2023-07-28T21:33:25-07:00"
},
"GeneralSpecs": {
"ProjectId": {
"Name": "nixitest1",
"GUID": "6e697869-7465-4737-9431-2e6b69636164",
"Revision": "rev?"
},
"Size": {
"X": 22.1,
"Y": 38.35
},
"LayerNumber": 2,
"BoardThickness": 1.6,
"Finish": "None"
},
"DesignRules": [
{
"Layers": "Outer",
"PadToPad": 0.15,
"PadToTrack": 0.15,
"TrackToTrack": 0.15,
"MinLineWidth": 0.2,
"TrackToRegion": 0.22,
"RegionToRegion": 0.22
}
],
"FilesAttributes": [
{
"Path": "nixitest1-F_Cu.gbr",
"FileFunction": "Copper,L1,Top",
"FilePolarity": "Positive"
},
{
"Path": "nixitest1-B_Cu.gbr",
"FileFunction": "Copper,L2,Bot",
"FilePolarity": "Positive"
},
{
"Path": "nixitest1-F_Paste.gbr",
"FileFunction": "SolderPaste,Top",
"FilePolarity": "Positive"
},
{
"Path": "nixitest1-B_Paste.gbr",
"FileFunction": "SolderPaste,Bot",
"FilePolarity": "Positive"
},
{
"Path": "nixitest1-F_Silkscreen.gbr",
"FileFunction": "Legend,Top",
"FilePolarity": "Positive"
},
{
"Path": "nixitest1-B_Silkscreen.gbr",
"FileFunction": "Legend,Bot",
"FilePolarity": "Positive"
},
{
"Path": "nixitest1-F_Mask.gbr",
"FileFunction": "SolderMask,Top",
"FilePolarity": "Negative"
},
{
"Path": "nixitest1-B_Mask.gbr",
"FileFunction": "SolderMask,Bot",
"FilePolarity": "Negative"
},
{
"Path": "nixitest1-Edge_Cuts.gbr",
"FileFunction": "Profile",
"FilePolarity": "Positive"
}
],
"MaterialStackup": [
{
"Type": "Legend",
"Name": "Top Silk Screen"
},
{
"Type": "SolderPaste",
"Name": "Top Solder Paste"
},
{
"Type": "SolderMask",
"Thickness": 0.01,
"Name": "Top Solder Mask"
},
{
"Type": "Copper",
"Thickness": 0.035,
"Name": "F.Cu"
},
{
"Type": "Dielectric",
"Thickness": 1.51,
"Material": "FR4",
"Name": "F.Cu/B.Cu",
"Notes": "Type: dielectric layer 1 (from F.Cu to B.Cu)"
},
{
"Type": "Copper",
"Thickness": 0.035,
"Name": "B.Cu"
},
{
"Type": "SolderMask",
"Thickness": 0.01,
"Name": "Bottom Solder Mask"
},
{
"Type": "SolderPaste",
"Name": "Bottom Solder Paste"
},
{
"Type": "Legend",
"Name": "Bottom Silk Screen"
}
]
}

1
nixitest1/kicad-libs Submodule

Submodule nixitest1/kicad-libs added at 02272eb0e4

24322
nixitest1/nixitest1.kicad_pcb
View File

File diff suppressed because it is too large Load Diff

2
nixitest1/nixitest1.kicad_prl
View File

@@ -3,10 +3,12 @@
"active_layer": 31,
"active_layer_preset": "",
"auto_track_width": true,
"hidden_netclasses": [],
"hidden_nets": [],
"high_contrast_mode": 0,
"net_color_mode": 1,
"opacity": {
"images": 0.6,
"pads": 1.0,
"tracks": 1.0,
"vias": 1.0,

83
nixitest1/nixitest1.kicad_pro
View File

@@ -1,5 +1,6 @@
{
"board": {
"3dviewports": [],
"design_settings": {
"defaults": {
"board_outline_line_width": 0.09999999999999999,
@@ -62,20 +63,26 @@
"rule_severities": {
"annular_width": "error",
"clearance": "error",
"connection_width": "warning",
"copper_edge_clearance": "error",
"copper_sliver": "warning",
"courtyards_overlap": "error",
"diff_pair_gap_out_of_range": "error",
"diff_pair_uncoupled_length_too_long": "error",
"drill_out_of_range": "error",
"duplicate_footprints": "warning",
"extra_footprint": "warning",
"footprint": "error",
"footprint_type_mismatch": "error",
"hole_clearance": "error",
"hole_near_hole": "error",
"invalid_outline": "error",
"isolated_copper": "warning",
"item_on_disabled_layer": "error",
"items_not_allowed": "error",
"length_out_of_range": "error",
"lib_footprint_issues": "warning",
"lib_footprint_mismatch": "warning",
"malformed_courtyard": "error",
"microvia_drill_out_of_range": "error",
"missing_courtyard": "ignore",
@@ -85,9 +92,14 @@
"padstack": "error",
"pth_inside_courtyard": "ignore",
"shorting_items": "error",
"silk_edge_clearance": "warning",
"silk_over_copper": "warning",
"silk_overlap": "warning",
"skew_out_of_range": "error",
"solder_mask_bridge": "error",
"starved_thermal": "error",
"text_height": "warning",
"text_thickness": "warning",
"through_hole_pad_without_hole": "error",
"too_many_vias": "error",
"track_dangling": "warning",
@@ -96,7 +108,6 @@
"unconnected_items": "error",
"unresolved_variable": "error",
"via_dangling": "warning",
"zone_has_empty_net": "error",
"zones_intersect": "error"
},
"rules": {
@@ -104,20 +115,65 @@
"allow_microvias": false,
"max_error": 0.005,
"min_clearance": 0.0,
"min_connection": 0.0,
"min_copper_edge_clearance": 0.0,
"min_hole_clearance": 0.25,
"min_hole_to_hole": 0.25,
"min_microvia_diameter": 0.19999999999999998,
"min_microvia_drill": 0.09999999999999999,
"min_resolved_spokes": 2,
"min_silk_clearance": 0.0,
"min_text_height": 0.7999999999999999,
"min_text_thickness": 0.08,
"min_through_hole_diameter": 0.19999999999999998,
"min_track_width": 0.19999999999999998,
"min_via_annular_width": 0.049999999999999996,
"min_via_diameter": 0.39999999999999997,
"solder_mask_clearance": 0.0,
"solder_mask_min_width": 0.0,
"solder_mask_to_copper_clearance": 0.0,
"use_height_for_length_calcs": true
},
"teardrop_options": [
{
"td_allow_use_two_tracks": true,
"td_curve_segcount": 5,
"td_on_pad_in_zone": false,
"td_onpadsmd": true,
"td_onroundshapesonly": false,
"td_ontrackend": false,
"td_onviapad": true
}
],
"teardrop_parameters": [
{
"td_curve_segcount": 0,
"td_height_ratio": 1.0,
"td_length_ratio": 0.5,
"td_maxheight": 2.0,
"td_maxlen": 1.0,
"td_target_name": "td_round_shape",
"td_width_to_size_filter_ratio": 0.9
},
{
"td_curve_segcount": 0,
"td_height_ratio": 1.0,
"td_length_ratio": 0.5,
"td_maxheight": 2.0,
"td_maxlen": 1.0,
"td_target_name": "td_rect_shape",
"td_width_to_size_filter_ratio": 0.9
},
{
"td_curve_segcount": 0,
"td_height_ratio": 1.0,
"td_length_ratio": 0.5,
"td_maxheight": 2.0,
"td_maxlen": 1.0,
"td_target_name": "td_track_end",
"td_width_to_size_filter_ratio": 0.9
}
],
"track_widths": [
0.0
],
@@ -130,7 +186,8 @@
"zones_allow_external_fillets": false,
"zones_use_no_outline": true
},
"layer_presets": []
"layer_presets": [],
"viewports": []
},
"boards": [],
"cvpcb": {
@@ -352,7 +409,7 @@
"net_settings": {
"classes": [
{
"bus_width": 12.0,
"bus_width": 12,
"clearance": 0.15,
"diff_pair_gap": 0.25,
"diff_pair_via_gap": 0.25,
@@ -366,10 +423,10 @@
"track_width": 0.2,
"via_diameter": 0.5,
"via_drill": 0.25,
"wire_width": 6.0
"wire_width": 6
},
{
"bus_width": 12.0,
"bus_width": 12,
"clearance": 0.15,
"diff_pair_gap": 0.25,
"diff_pair_via_gap": 0.25,
@@ -378,21 +435,25 @@
"microvia_diameter": 0.2,
"microvia_drill": 0.1,
"name": "Thicc",
"nets": [
"+5V"
],
"pcb_color": "rgba(0, 0, 0, 0.000)",
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.3,
"via_diameter": 0.5,
"via_drill": 0.25,
"wire_width": 6.0
"wire_width": 6
}
],
"meta": {
"version": 2
"version": 3
},
"net_colors": null
"net_colors": null,
"netclass_assignments": null,
"netclass_patterns": [
{
"netclass": "Thicc",
"pattern": "+5V"
}
]
},
"pcbnew": {
"last_paths": {

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