sci-electronics/yosys: version bump

2024-09-03 09:53:00 -07:00
parent 72edd41909
commit 2fcd2f4d37
2 changed files with 2 additions and 2 deletions
--- a/sci-electronics/yosys/yosys-0.45.ebuild
+++ b/sci-electronics/yosys/yosys-0.45.ebuild
@@ -5,7 +5,7 @@ inherit git-r3
 DESCRIPTION="framework for Verilog RTL synthesis"
 HOMEPAGE="http://www.clifford.at/yosys/"
 EGIT_REPO_URI=https://github.com/YosysHQ/yosys
-EGIT_COMMIT=$P
+EGIT_COMMIT=$PV
 LICENSE=ISC
 SLOT=0
 KEYWORDS=amd64