diff --git a/metadata/md5-cache/sci-electronics/yosys-0.47 b/metadata/md5-cache/sci-electronics/yosys-0.48
similarity index 89%
rename from metadata/md5-cache/sci-electronics/yosys-0.47
rename to metadata/md5-cache/sci-electronics/yosys-0.48
index 4a588676..62a9bb03 100644
--- a/metadata/md5-cache/sci-electronics/yosys-0.47
+++ b/metadata/md5-cache/sci-electronics/yosys-0.48
@@ -10,4 +10,4 @@ LICENSE=ISC
 PROPERTIES=live
 SLOT=0
 _eclasses_=git-r3	875eb471682d3e1f18da124be97dcc81
-_md5_=180368382f349638912c4258ad87dc0f
+_md5_=c31438e098c25b49fe21cb1e0ab58f72
diff --git a/sci-electronics/yosys/yosys-0.47.ebuild b/sci-electronics/yosys/yosys-0.48.ebuild
similarity index 96%
rename from sci-electronics/yosys/yosys-0.47.ebuild
rename to sci-electronics/yosys/yosys-0.48.ebuild
index be7f5e89..74f529fa 100644
--- a/sci-electronics/yosys/yosys-0.47.ebuild
+++ b/sci-electronics/yosys/yosys-0.48.ebuild
@@ -5,7 +5,7 @@ inherit git-r3
 DESCRIPTION="framework for Verilog RTL synthesis"
 HOMEPAGE="http://www.clifford.at/yosys/"
 EGIT_REPO_URI=https://github.com/YosysHQ/yosys
-EGIT_COMMIT=$PV
+EGIT_COMMIT=v$PV
 LICENSE=ISC
 SLOT=0
 KEYWORDS=amd64