Remove pattern parameter (moved to outline file)

2016-02-04 16:24:14 +03:00
parent 08ee4b4dc3
commit ffbba64423
5 changed files with 1 additions and 5 deletions
--- a/altera/5m1270zt144.yaml
+++ b/altera/5m1270zt144.yaml
@@ -140,5 +140,4 @@ parts:
  Power: VCCINT, GNDINT

 housing:
-  pattern: QFP
  outline: JEDEC MS-026 BFB
--- a/ti/iso72x.yaml
+++ b/ti/iso72x.yaml
@@ -22,7 +22,6 @@ schematic:
 housing: SOIC8

 SOIC8:
-  pattern: SOIC
  outline: JEDEC MS-012 AA
  suffix: D, MD

--- a/ti/sn74lvc1g07dbv.yaml
+++ b/ti/sn74lvc1g07dbv.yaml
@@ -9,5 +9,4 @@ pinout:
  NC: 1

 housing:
-  pattern: SOT
  outline: JEDEC MO-178 AA
--- a/ti/sn74lvc1g07dck.yaml
+++ b/ti/sn74lvc1g07dck.yaml
@@ -2,5 +2,4 @@ name: SN74LVC1G07DCK
 base: SN74LVC1G07DBV

 housing:
-  pattern: SOT
  outline: JEDEC MO-203 AA
--- a/ti/sn74lvc1g07drl.yaml
+++ b/ti/sn74lvc1g07drl.yaml
@@ -2,7 +2,7 @@ name: SN74LVC1G07DRL
 base: SN74LVC1G07DBV

 housing:
-  pattern: SOT
+  pattern: SOT23
  bodyWidth: 1.1-1.3
  bodyLength: 1.5-1.7
  height: 0.5-0.6