Use plated slots and adjust 5V trace to be above the GND plane

Signed-off-by: Stefan Agner <stefan@agner.ch>
This commit is contained in:
Stefan Agner
2021-04-27 23:48:06 +02:00
parent 015d516feb
commit adc977f8c1
4 changed files with 2259 additions and 2347 deletions

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@@ -1,6 +1,6 @@
{
"board": {
"active_layer": 36,
"active_layer": 0,
"active_layer_preset": "All Layers",
"auto_track_width": false,
"hidden_nets": [],

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@@ -80,6 +80,8 @@
"clearance|36900000|52020000|1e5277ff-2806-4c72-b9fc-f481d088362c|d64961f5-517b-4490-b68f-140e594549f6",
"clearance|38900000|52720000|37a9dcee-cf03-4653-9ee1-05cf43670197|931c23fe-5f56-4f5a-bff5-77f1cb024eb6",
"clearance|44400000|52020000|ff995202-2ab7-4018-96ca-c0ccb9427b2f|07fd0146-3d92-4406-b764-00cf12c2f9a9",
"courtyards_overlap|139466001|62992000|002acccc-be8a-4e21-8de4-c1e92b9d1a43|b3ef7ab8-c316-4700-9910-38dbd54503b6",
"courtyards_overlap|139974001|96774000|9e4674ec-ef29-4b71-bc7f-598a5332477c|b3ef7ab8-c316-4700-9910-38dbd54503b6",
"diff_pair_gap_out_of_range|115567511|124550605|1bbd4b53-e008-4bfb-8c5b-a9ddf0ada7d0|c35ac83e-d9e1-424e-abf7-ce6834fa8260"
],
"meta": {
@@ -110,8 +112,8 @@
"padstack": "error",
"pth_inside_courtyard": "ignore",
"shorting_items": "error",
"silk_over_copper": "warning",
"silk_overlap": "warning",
"silk_over_copper": "ignore",
"silk_overlap": "ignore",
"skew_out_of_range": "error",
"too_many_vias": "error",
"track_dangling": "warning",
@@ -560,7 +562,7 @@
"idf": "",
"netlist": "",
"specctra_dsn": "",
"step": "LightBlue_0.2pre3.step",
"step": "LightBlue_0.2pre4.step",
"vrml": ""
},
"page_layout_descr_file": ""

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@@ -1,5 +1,5 @@
(footprint "DrillSlot_Plated_5x3mm" (version 20210228) (generator pcbnew) (layer "F.Cu")
(tedit 6088523E)
(tedit 608882D4)
(fp_text reference "REF**" (at 0 -0.5 unlocked) (layer "F.SilkS") hide
(effects (font (size 1 1) (thickness 0.15)))
(tstamp e52ad8c7-a210-4717-b2d0-3ea424f7e6c1)
@@ -12,5 +12,5 @@
(effects (font (size 1 1) (thickness 0.15)))
(tstamp af8338d2-63c8-49c7-8f3f-eba4d7a7adc3)
)
(pad "" np_thru_hole oval (at 0 0) (size 5.3 3.3) (drill oval 5 3) (layers F&B.Cu *.Mask) (tstamp f9631126-7144-462d-97fa-3fe4a6d42d04))
(pad "" thru_hole oval (at 0 0) (size 5.3 3.3) (drill oval 5 3) (layers *.Cu *.Mask) (tstamp f9631126-7144-462d-97fa-3fe4a6d42d04))
)