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Rework PCB Layout

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Adjust some high level placement like M.2 or CM4 and heatsink. Remove
all traces and vias since most of the layouting has to be redone
anyways.

Signed-off-by: Stefan Agner <stefan@agner.ch>
This commit is contained in:
Stefan Agner
2021-04-16 17:51:59 +02:00
parent 818c132a38
commit c01bfa5c9e
6 changed files with 1108 additions and 6428 deletions
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2
Ethernet.kicad_sch
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@@ -2507,8 +2507,8 @@
)
)
(bus_alias "ETH" (members "TD1+" "TD1-" "TD2+" "TD2-" "TD3+" "TD3-" "TD4+" "TD4-" "LED_YELLOW" "LED_GREEN"))
(bus_alias "PoE" (members "VC1" "VC2" "VC3" "VC4"))
(bus_alias "ETH" (members "TD1+" "TD1-" "TD2+" "TD2-" "TD3+" "TD3-" "TD4+" "TD4-" "LED_YELLOW" "LED_GREEN"))
(junction (at 153.67 80.01) (diameter 0.9144) (color 0 0 0 0))
(junction (at 177.8 130.81) (diameter 0.9144) (color 0 0 0 0))
(junction (at 179.07 139.7) (diameter 0.9144) (color 0 0 0 0))