Commit Graph

12 Commits

Author SHA1 Message Date
Stefan Agner
574e6d401b Add UKCA mark to bottom silk screen
Fixes: #46

Signed-off-by: Stefan Agner <stefan@agner.ch>
2022-03-30 14:34:42 +02:00
Stefan Agner
e0e2b8ecd0 Bump revision to 1.2
Bump revision to 1.2 in Schematic/PCB sheets and update the date.

Signed-off-by: Stefan Agner <stefan@agner.ch>
2022-02-15 22:05:53 +01:00
Stefan Agner
a298a6461d Adjust/fix silkscreen
- Place reference properly
- Move and update Wireless smart-home text
- Move and update PoE+ text
- Readd symbols and back silkscreen (with proper attributes)

Signed-off-by: Stefan Agner <stefan@agner.ch>
2022-02-15 21:40:26 +01:00
Dominik Sliwa
42cd10c86b Moved PoE few mm lower
In order to accomodate the C93 next to the transformer.
Added top layer GND1 pour under the transformer
shortened the GNDS path.

Signed-off-by: Dominik Sliwa <dominik@sliwa.io>
2022-02-15 20:59:48 +01:00
Dominik Sliwa
9354729d76 Zone cleanup
Cleanup some fill zones.
Updated the Transformer symbol with pin 4, connected to +48V for better
zone fill.
fixed top/bottom transition for the DC_IN_F
Added some gnd vias

Signed-off-by: Dominik Sliwa <dominik@sliwa.io>
2022-02-15 12:02:54 +01:00
Dominik Sliwa
8fd9133aec PoE EMI optimization
Modified PoE layout to account for GNDS-GND1 flow
and repositioned the noise retern capacitor.
Snubber was corrected for the transformer used and the switching
frequency. Some components were removed.
PoE Input filter was adjusted.

3.3 and 5V DCDC capacitor layout was optimised and unused components
were removed.

Signed-off-by: Dominik Sliwa <dominik@sliwa.io>
2022-02-15 00:29:21 +01:00
Dominik Sliwa
f5f77585a0 Move J11 5.08mm up
Moved the reduced rPI hat conenctor to accomodate bigger hats

Signed-off-by: Dominik Sliwa <dominik@sliwa.io>
2022-02-05 18:53:46 +01:00
Stefan Agner
8f5fade02a Various minor silk screen/PCB tweaks
- Fix edge cut on lower right corner to make board size exact
- Update board charactristics
- Set grid origin back to 30, 30
- Update M.2 expansion silk screen (remove AI accelerator hint)
- Various silk screen reference designator fixes/improvements
- Add ESD warning logo

Signed-off-by: Stefan Agner <stefan@agner.ch>
2022-01-10 11:19:45 +01:00
Dominik Sliwa
da1b852f0a Cleanup DRC violations
Signed-off-by: Dominik Sliwa <dominik@sliwa.io>
2022-01-10 08:59:52 +01:00
Stefan Agner
f4d8d9d038 Silkscreen fixes/small BOM adjustments
- Update silk screen reference designators
- Update backside silk screen for Yellow revision 1.1
- Set U21 (SOIC-8 RTC) to assemble and U25 (MSOP-8) as DNP
- Update heatsink footprint to add heatsink outline to silk screen (#44)
- Mark orientation of D26, D27, D28 and D29 (fixes #39)
- Use pin-header footprint for PoE selector J13, it is now JP5

Signed-off-by: Stefan Agner <stefan@agner.ch>
2022-01-09 22:18:52 +01:00
Dominik Sliwa
04ea9a070b Optimise PoE layout
Signed-off-by: Dominik Sliwa <dominik@sliwa.io>
2022-01-09 12:11:04 +01:00
Stefan Agner
019c9efdda Rename Amber to Yellow everywhere
Signed-off-by: Stefan Agner <stefan@agner.ch>
2022-01-06 17:08:55 +01:00