Add BD9D321EFJ to the symbol library and align it properly to the
1.27mm/0.050inch grid. Make sure to align the instances U15/U16
correctly as well as the complete Power schematic.
With that GND is now correctly connected to Pin 5 of U16.
Fixes: #27
Signed-off-by: Stefan Agner <stefan@agner.ch>
The current trace width/diff pair gap are impedance matched for the
JLC7628 stackup. Change the board setup to reflect that stackup.
Signed-off-by: Stefan Agner <stefan@agner.ch>
Switch the SiLabs Radio module from MGM210PB32JIA2 to MGM210PA32JIA2.
The PA version has no secure vault but is slightly cheaper. It is
unlikely that we use the secure vault anytime soon, so let's use the PA
version.
Signed-off-by: Stefan Agner <stefan@agner.ch>
The MOSFET 3D model did not fit the footprint, select a matching model.
Also adjust 5V routing to avoid an unnecessary via.
Signed-off-by: Stefan Agner <stefan@agner.ch>
Move the RPi LEDs closer to the CM4 to make space for PCB Art in the top
right corner.
Fix Silkscreen accross the whole board.
Signed-off-by: Stefan Agner <stefan@agner.ch>
Deal with DRC warnings by either ignoring (like courtyard overlap of
fiducials) or fixing (removing duplicate vias).
Also use a shorter route for SWDIO.
Signed-off-by: Stefan Agner <stefan@agner.ch>
Move the LP5569RTWR LED controller so it doesn't interfere with the
LED light diffuser if we decide to make it sit directly on the PCB.
Signed-off-by: Stefan Agner <stefan@agner.ch>
Rotate jumpers J2 through J4 by 90° degrees. This makes all jumper
orient the same and makes space for silk screen.
Signed-off-by: Stefan Agner <stefan@agner.ch>
All new footprints refer to the 3D model by using KICAD6_3DMODEL_DIR.
Update the footprints in .kicad_pcb to do the same.
Signed-off-by: Stefan Agner <stefan@agner.ch>
Make the PoE class selector pin header horizontal. Also move battery
holder a bit south and extend PoE GND slightly to make room.
Also fix placements of silk screen.
Signed-off-by: Stefan Agner <stefan@agner.ch>
updates
schematic:
-change usb current protection IC to 1.5A
-Added low-pass filter to the audio output
-PoE fixed primary windings polarity
-added option to select poe class with a jumper (between 3 and 4)
-fixes in poe design
-added testpoints
-added virtual hirose df40c connectors for pick and place use
lightblue.pretty:
-added fake DF40C footprint for pick and place and 3d model purposes
Signed-off-by: Dominik Sliwa <dominik@sliwa.io>
Make the heat sink footprint to represent the real heatsink without
rotation and the correct outer dimension (56x56mm). Also position the
heatsink centered on the CM4 SoC.
Signed-off-by: Stefan Agner <stefan@agner.ch>
This makes sure that the origin aligns with the top left corner of the
board when importing the PCB using FreeCAD KiCadStepUp.
Signed-off-by: Stefan Agner <stefan@agner.ch>
2.2uF/100V are not really available in a 0805 package. This part of
the PoE design a 25V rating is sufficent.
Fixes: #22
Signed-off-by: Stefan Agner <stefan@agner.ch>
- Add multiple ventilation slots (move some traces for space)
- Add Home Assistant logo to the back
- Add Nabu Casa logo on the front
- Fixup reference designators placement in several cases
Signed-off-by: Stefan Agner <stefan@agner.ch>
Order some relevant reference designator. Use JP for all jumpers. Place
silkcreen neatly. Add some custom silk screen. Remove heat sink corner
marks on silk screen.
Signed-off-by: Stefan Agner <stefan@agner.ch>
Changes:
Footrints:
-Modified DC Jack to accomodate CUI PJ-002A
-Modified RJ45 to increase clearance between shield and poe pins
-Modified m.2 mounting pads to avoid drc errors
Schematic:
-usb-c facing usb mux is supplied by +3v3VP
-added misc. capacitors
PCB
-min. annular ring for vias set to 0.125 from 0.2
Signed-off-by: Dominik Sliwa <dominik@sliwa.io>
Use JLC7628 impedance values to get more options in color selection.
Also this leads to slightly wider traces typically, and it will be
easier to switch back to JLC2313 or the like than the other way around.
Also swap placing of HDMI/SW2 and rotate the heatsink by 90° for easier
routing.
Signed-off-by: Stefan Agner <stefan@agner.ch>
Change the length and positioning of the buttons and start layouting a
bit. Move components where needed.
Signed-off-by: Stefan Agner <stefan@agner.ch>
Use minimal track width/gap of 0.127mm. Use impedance calculated using
the JLCPCB calculator for the 85Ohm/90Ohm differential pairs and 50Ohm
single trace.
For the 100Ohm pair the JLCPCB calculator does not allow to specify a
track gap which leads to a track width of 0.127mm or bigger. Hence for
this I used https://www.mantaro.com/resources/impedance-calculator.htm
(with Er 4.05, h 0.095, t 0.035).
Also use vias of 0.45/0.2mm by default.
Fixes: #6
Signed-off-by: Stefan Agner <stefan@agner.ch>
The current M2.5 holes work well for the soldered nuts from JAE
(SM3ZS067U310-NUT1-R1800). However, we are going to use a custom
standoff with a M2 thread (nut) and a screw to mechanically secure the
NVMe. The nut will have a border to fit the hole. That the standoff
still can fit a M2 thread we need M3 holes.
Signed-off-by: Stefan Agner <stefan@agner.ch>
Adjust some high level placement like M.2 or CM4 and heatsink. Remove
all traces and vias since most of the layouting has to be redone
anyways.
Signed-off-by: Stefan Agner <stefan@agner.ch>
Instead of using VBUS to power CP2102N use the main/NVMe 3.3V supply.
This makes sure that the device stays powered during reset, while making
sure the CP2102N is always powered and doesn't backfeed if no USB is
plugged in.
Signed-off-by: Stefan Agner <stefan@agner.ch>
