5 Commits

Author	SHA1	Message	Date
Stefan Agner	8f5fade02a	Various minor silk screen/PCB tweaks ... - Fix edge cut on lower right corner to make board size exact - Update board charactristics - Set grid origin back to 30, 30 - Update M.2 expansion silk screen (remove AI accelerator hint) - Various silk screen reference designator fixes/improvements - Add ESD warning logo Signed-off-by: Stefan Agner <stefan@agner.ch>	2022-01-10 11:19:45 +01:00
Dominik Sliwa	da1b852f0a	Cleanup DRC violations ... Signed-off-by: Dominik Sliwa <dominik@sliwa.io>	2022-01-10 08:59:52 +01:00
Stefan Agner	f4d8d9d038	Silkscreen fixes/small BOM adjustments ... - Update silk screen reference designators - Update backside silk screen for Yellow revision 1.1 - Set U21 (SOIC-8 RTC) to assemble and U25 (MSOP-8) as DNP - Update heatsink footprint to add heatsink outline to silk screen (#44) - Mark orientation of D26, D27, D28 and D29 (fixes #39) - Use pin-header footprint for PoE selector J13, it is now JP5 Signed-off-by: Stefan Agner <stefan@agner.ch>	2022-01-09 22:18:52 +01:00
Dominik Sliwa	04ea9a070b	Optimise PoE layout ... Signed-off-by: Dominik Sliwa <dominik@sliwa.io>	2022-01-09 12:11:04 +01:00
Stefan Agner	019c9efdda	Rename Amber to Yellow everywhere ... Signed-off-by: Stefan Agner <stefan@agner.ch>	2022-01-06 17:08:55 +01:00