Commit Graph

4 Commits

Author SHA1 Message Date
Dominik Sliwa
8fd9133aec PoE EMI optimization
Modified PoE layout to account for GNDS-GND1 flow
and repositioned the noise retern capacitor.
Snubber was corrected for the transformer used and the switching
frequency. Some components were removed.
PoE Input filter was adjusted.

3.3 and 5V DCDC capacitor layout was optimised and unused components
were removed.

Signed-off-by: Dominik Sliwa <dominik@sliwa.io>
2022-02-15 00:29:21 +01:00
Dominik Sliwa
da1b852f0a Cleanup DRC violations
Signed-off-by: Dominik Sliwa <dominik@sliwa.io>
2022-01-10 08:59:52 +01:00
Stefan Agner
f4d8d9d038 Silkscreen fixes/small BOM adjustments
- Update silk screen reference designators
- Update backside silk screen for Yellow revision 1.1
- Set U21 (SOIC-8 RTC) to assemble and U25 (MSOP-8) as DNP
- Update heatsink footprint to add heatsink outline to silk screen (#44)
- Mark orientation of D26, D27, D28 and D29 (fixes #39)
- Use pin-header footprint for PoE selector J13, it is now JP5

Signed-off-by: Stefan Agner <stefan@agner.ch>
2022-01-09 22:18:52 +01:00
Stefan Agner
019c9efdda Rename Amber to Yellow everywhere
Signed-off-by: Stefan Agner <stefan@agner.ch>
2022-01-06 17:08:55 +01:00