-Snubber circuit under ecrtail load condition can dissipate more power
then the resistor can handle, increased the resistor size and added one
more in parallel
-Increased size of some of the 12V input capacitors
-Use 3.3Vp instead of 3.3V generated by the RPi for LED, RTC, Radio, Fan
control and RPi reduced hat connector
-PoE pri/sec capacitor value changed
Signed-off-by: Dominik Sliwa <dominik@sliwa.io>
decreased coupling between poe lines and the gnd plane
added vias to stich main gnd planes
decreased the peak current through the transformer
inductor based pi filter on the poe output
decreased coupling to gnd of the poe "noise path"
added parallel mosfet capacitance to poe
moved fb line fo the dcdcs away from inductors
Signed-off-by: Dominik Sliwa <dominik@sliwa.io>
Increment to sub-version v1.2. Main changes are:
- Back and front silk screen
- LED resistors
There are no changes in the layout and any critical components.
Signed-off-by: Stefan Agner <stefan@agner.ch>
- Fix edge cut on lower right corner to make board size exact
- Update board charactristics
- Set grid origin back to 30, 30
- Update M.2 expansion silk screen (remove AI accelerator hint)
- Various silk screen reference designator fixes/improvements
- Add ESD warning logo
Signed-off-by: Stefan Agner <stefan@agner.ch>
- Update silk screen reference designators
- Update backside silk screen for Yellow revision 1.1
- Set U21 (SOIC-8 RTC) to assemble and U25 (MSOP-8) as DNP
- Update heatsink footprint to add heatsink outline to silk screen (#44)
- Mark orientation of D26, D27, D28 and D29 (fixes#39)
- Use pin-header footprint for PoE selector J13, it is now JP5
Signed-off-by: Stefan Agner <stefan@agner.ch>
Order some relevant reference designator. Use JP for all jumpers. Place
silkcreen neatly. Add some custom silk screen. Remove heat sink corner
marks on silk screen.
Signed-off-by: Stefan Agner <stefan@agner.ch>
Add the CM4 board to board connectors using separate symbols. This is a
bit a hack, but makes sure two pieces appear in the BOM.
Also, this seems to upgrade all the schematic to the latest KiCad
schematic version.
Signed-off-by: Stefan Agner <stefan@agner.ch>
The 1- at the start of the part number denotes M-Key which is a rather
important distinction. Fix the footprint name.
Signed-off-by: Stefan Agner <stefan@agner.ch>
- Fix footprint for 02x05 pin header
- Add footprint for Bourns SDR1006 Inductor (PoE)
- Define footprints for inductors
- Define footprints for ferrite beads
- Define footprint for fuse
- Define footprints for all resistors
- Define footprints for SD card and other components
- Switch ON Semi NCP114MX with TI TLV73333PDBV
Signed-off-by: Stefan Agner <stefan@agner.ch>
- Moved PoE to a seperate sheet and finished design
- Started using Config field for Variants and DNP flag
- Fix-ups
- Added Wurth 749119550 and TI TPS23734 to the symbol library
- Changed RTC from PCF8563 to PCF85063
Signed-off-by: Dominik Sliwa <dominik@sliwa.io>
-Added sdcard sheet and SD bus
-changed main i2c bus
-added 1.8V and 3.3V connection to CM4
-removed clk32 from led driver
-fixed PCM interface Data pin
Signed-off-by: Dominik Sliwa <dominik@sliwa.io>
-Added AP64501SP-13 library symbol
-Initial power supplies schematics
-Increased capacitance for PCIe socket
-Connections between sheets
Signed-off-by: Dominik Sliwa <dominik@sliwa.io>
-Added net classes for controlled impedance traces
-Added power hierarchical sheet
-Initial USB subsystem schematic
-Added multiple bus definitions (usb, pcie, i2c etc.)
-Fixed busses use
-Added LDO for audio analog rails
Signed-off-by: Dominik Sliwa <dominik@sliwa.io>
