- Update silk screen reference designators
- Update backside silk screen for Yellow revision 1.1
- Set U21 (SOIC-8 RTC) to assemble and U25 (MSOP-8) as DNP
- Update heatsink footprint to add heatsink outline to silk screen (#44)
- Mark orientation of D26, D27, D28 and D29 (fixes#39)
- Use pin-header footprint for PoE selector J13, it is now JP5
Signed-off-by: Stefan Agner <stefan@agner.ch>
-Fixed upstream diff pair polarity
-added optional inverer for the USB power switch enable pin
Design now supports both AP2181 and AP2191
Signed-off-by: Dominik Sliwa <dominik@sliwa.io>
Run annotation again which just updated some net names. Address various
DRC issues like courtyard violence and exclude the remaining DRC errors.
Signed-off-by: Stefan Agner <stefan@agner.ch>
- Change FL1 to be Murata Electronics DLW5BTM102SQ2. This version is not
automotive approved. It is cheaper and has better availability
currently.
Signed-off-by: Stefan Agner <stefan@agner.ch>
- U7: Define Manufacturer/PartNumber
- J13: Define Manufacturer/PartNumber
- L2: Fix PartNumber (remove unprintable characters)
- C85: Change to our preferred supplier Nichicon
- J9: DNP (not used by default, avoid potential issues with FCC approval)
- Y1/Y2: Define frequency and load capacitance in value
- JP1: Use sensible part value
- C106: Fix Config field
- Remove heat sink and CM4 from BOM (handled in product assembly BOM)
Signed-off-by: Stefan Agner <stefan@agner.ch>
PoE
-Added a common mode filter on the input
-FB filter on the output side
-12V in now disables the poe with the DEN pin
-DT is now disabled
-PSRS is now disabled
-move to 1210 resistors for resistors identified in thermal testing
-DTHR is now enabled in default BoM
-some resistor values were adjusted
-some caps were moved to the common power supply section
USB:
-USB Hub 1.8V rail have capacitors added
Signed-off-by: Dominik Sliwa <dominik@sliwa.io>
updates
schematic:
-change usb current protection IC to 1.5A
-Added low-pass filter to the audio output
-PoE fixed primary windings polarity
-added option to select poe class with a jumper (between 3 and 4)
-fixes in poe design
-added testpoints
-added virtual hirose df40c connectors for pick and place use
lightblue.pretty:
-added fake DF40C footprint for pick and place and 3d model purposes
Signed-off-by: Dominik Sliwa <dominik@sliwa.io>
2.2uF/100V are not really available in a 0805 package. This part of
the PoE design a 25V rating is sufficent.
Fixes: #22
Signed-off-by: Stefan Agner <stefan@agner.ch>
Order some relevant reference designator. Use JP for all jumpers. Place
silkcreen neatly. Add some custom silk screen. Remove heat sink corner
marks on silk screen.
Signed-off-by: Stefan Agner <stefan@agner.ch>
Changes:
Footrints:
-Modified DC Jack to accomodate CUI PJ-002A
-Modified RJ45 to increase clearance between shield and poe pins
-Modified m.2 mounting pads to avoid drc errors
Schematic:
-usb-c facing usb mux is supplied by +3v3VP
-added misc. capacitors
PCB
-min. annular ring for vias set to 0.125 from 0.2
Signed-off-by: Dominik Sliwa <dominik@sliwa.io>
- Replace unusual/high value ceramics with lower value in parallel
- Use the same protection Shottky Diode in PoE as in regular input
(B340LB-13-F)
- Replace PoE rectifier Diodes with B1100-13-F
- Replace PoE Inductor (SRN6045TA-3R3Y) with the same part from 5V power
supply (Taiyo Yuden NRS8030T3R3MJGJ)
- Correctly specify Pulse Electronics transformer
Signed-off-by: Stefan Agner <stefan@agner.ch>
- Use Diodes B2100-13-F consistently
- Define part for pin headers
- Replace N-Channel MOSFET for PoE with BSZ440N10NS3GATMA1
- Define Input protection MOSFET DMP3013SFV-7
Signed-off-by: Stefan Agner <stefan@agner.ch>
