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Update icestorm project to match APIO project.

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This commit is contained in:
Thomas Daede
2018-07-12 17:32:02 -07:00
parent c02b2e908e
commit 2f01834277
5 changed files with 127 additions and 100 deletions
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6
icestorm_template/Makefile
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@@ -14,7 +14,7 @@
# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
PROJ = TinyFPGA_B
PROJ = top
PIN_DEF = pins.pcf
DEVICE = lp8k
@@ -49,11 +49,11 @@ all: $(PROJ).rpt $(PROJ).bin
vvp -N $< +vcd=$@
prog: $(PROJ).bin
iceprog $<
tinyprog -p $<
sudo-prog: $(PROJ).bin
@echo 'Executing prog as root!!!'
sudo iceprog $<
sudo tinyprog -p $<
clean:
rm -f $(PROJ).blif $(PROJ).asc $(PROJ).rpt $(PROJ).bin

6
icestorm_template/README.md
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@@ -27,7 +27,7 @@ make -j$(nproc)
sudo make install
cd ..
pip install --user tinyprog
```
Copy the icestorm_template directory to a new project directory with a name of your choosing:
@@ -42,9 +42,9 @@ cd ~/my_tinyfpga_project
make
```
The programmer script lives in this repo in [programmer/tinyfpgab.py](https://github.com/tinyfpga/TinyFPGA-B-Series/blob/master/programmer/tinyfpgab.py) Program the TinyFPGA B-series board with the bitstream:
Program the TinyFPGA B-series board with the bitstream:
```shell
python $TINYFPGA_B_REPO/programmer/tinyfpgab.py --program TinyFPGA_B.bin
make prog
```

67
icestorm_template/TinyFPGA_B.v
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@@ -1,67 +0,0 @@
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
///
/// Top-Level Verilog Module
///
/// Only include pins the design is actually using. Make sure that the pin is
/// given the correct direction: input vs. output vs. inout
///
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
module TinyFPGA_B (
output pin1_usb_dp,
output pin2_usb_dn,
input pin3_clk_16mhz,
//inout pin4,
//inout pin5,
//inout pin6,
//inout pin7,
//inout pin8,
//inout pin9,
//inout pin10,
//inout pin11,
//inout pin12,
output pin13,
//inout pin14_sdo,
//inout pin15_sdi,
//inout pin16_sck,
//inout pin17_ss,
//inout pin18,
//inout pin19,
//inout pin20,
//inout pin21,
//inout pin22,
//inout pin23,
//inout pin24
);
reg [23:0] counter;
always @(posedge pin3_clk_16mhz) counter <= counter + 1;
/// left side of board
assign pin1_usb_dp = 1'b0;
assign pin2_usb_dn = 1'b0;
//assign pin4 = 1'bz;
//assign pin5 = 1'bz;
//assign pin6 = 1'bz;
//assign pin7 = 1'bz;
//assign pin8 = 1'bz;
//assign pin9 = 1'bz;
//assign pin10 = 1'bz;
//assign pin11 = 1'bz;
//assign pin12 = 1'bz;
assign pin13 = counter[23];
/// right side of board
//assign pin14_sdo = 1'bz;
//assign pin15_sdi = 1'bz;
//assign pin16_sck = 1'bz;
//assign pin17_ss = 1'bz;
//assign pin18 = 1'bz;
//assign pin19 = 1'bz;
//assign pin20 = 1'bz;
//assign pin21 = 1'bz;
//assign pin22 = 1'bz;
//assign pin23 = 1'bz;
//assign pin24 = 1'bz;
endmodule

121
icestorm_template/pins.pcf
View File

@@ -1,27 +1,94 @@
### left side of board
set_io --warn-no-port pin1_usb_dp A3
set_io --warn-no-port pin2_usb_dn A4
set_io --warn-no-port pin3_clk_16mhz B4
set_io --warn-no-port pin4 B2
set_io --warn-no-port pin5 A2
set_io --warn-no-port pin6 A1
set_io --warn-no-port pin7 B1
set_io --warn-no-port pin8 C1
set_io --warn-no-port pin9 D1
set_io --warn-no-port pin10 E1
set_io --warn-no-port pin11 G1
set_io --warn-no-port pin12 H1
set_io --warn-no-port pin13 J1
### right side of board
set_io --warn-no-port pin14_sdo G6
set_io --warn-no-port pin15_sdi H7
set_io --warn-no-port pin16_sck G7
set_io --warn-no-port pin17_ss F7
set_io --warn-no-port pin18 D9
set_io --warn-no-port pin19 C9
set_io --warn-no-port pin20 E8
set_io --warn-no-port pin21 A9
set_io --warn-no-port pin22 A8
set_io --warn-no-port pin23 A7
set_io --warn-no-port pin24 A6
###############################################################################
#
# TinyFPGA BX constraint file (.pcf)
#
###############################################################################
#
# Copyright (c) 2018, Luke Valenty
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are met:
#
# 1. Redistributions of source code must retain the above copyright notice, this
# list of conditions and the following disclaimer.
# 2. Redistributions in binary form must reproduce the above copyright notice,
# this list of conditions and the following disclaimer in the documentation
# and/or other materials provided with the distribution.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
# ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# The views and conclusions contained in the software and documentation are those
# of the authors and should not be interpreted as representing official policies,
# either expressed or implied, of the <project name> project.
#
###############################################################################
####
# TinyFPGA BX information: https://github.com/tinyfpga/TinyFPGA-BX/
####
# Left side of board
set_io --warn-no-port PIN_1 A2
set_io --warn-no-port PIN_2 A1
set_io --warn-no-port PIN_3 B1
set_io --warn-no-port PIN_4 C2
set_io --warn-no-port PIN_5 C1
set_io --warn-no-port PIN_6 D2
set_io --warn-no-port PIN_7 D1
set_io --warn-no-port PIN_8 E2
set_io --warn-no-port PIN_9 E1
set_io --warn-no-port PIN_10 G2
set_io --warn-no-port PIN_11 H1
set_io --warn-no-port PIN_12 J1
set_io --warn-no-port PIN_13 H2
# Right side of board
set_io --warn-no-port PIN_14 H9
set_io --warn-no-port PIN_15 D9
set_io --warn-no-port PIN_16 D8
set_io --warn-no-port PIN_17 C9
set_io --warn-no-port PIN_18 A9
set_io --warn-no-port PIN_19 B8
set_io --warn-no-port PIN_20 A8
set_io --warn-no-port PIN_21 B7
set_io --warn-no-port PIN_22 A7
set_io --warn-no-port PIN_23 B6
set_io --warn-no-port PIN_24 A6
# SPI flash interface on bottom of board
set_io --warn-no-port SPI_SS F7
set_io --warn-no-port SPI_SCK G7
set_io --warn-no-port SPI_IO0 G6
set_io --warn-no-port SPI_IO1 H7
set_io --warn-no-port SPI_IO2 H4
set_io --warn-no-port SPI_IO3 J8
# General purpose pins on bottom of board
set_io --warn-no-port PIN_25 G1
set_io --warn-no-port PIN_26 J3
set_io --warn-no-port PIN_27 J4
set_io --warn-no-port PIN_28 G9
set_io --warn-no-port PIN_29 J9
set_io --warn-no-port PIN_30 E8
set_io --warn-no-port PIN_31 J2
# LED
set_io --warn-no-port LED B3
# USB
set_io --warn-no-port USBP B4
set_io --warn-no-port USBN A4
set_io --warn-no-port USBPU A3
# 16MHz clock
set_io --warn-no-port CLK B2 # input

27
icestorm_template/top.v Normal file
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@@ -0,0 +1,27 @@
// look in pins.pcf for all the pin names on the TinyFPGA BX board
module top (
input CLK, // 16MHz clock
output LED, // User/boot LED next to power LED
output USBPU // USB pull-up resistor
);
// drive USB pull-up resistor to '0' to disable USB
assign USBPU = 0;
////////
// make a simple blink circuit
////////
// keep track of time and location in blink_pattern
reg [25:0] blink_counter;
// pattern that will be flashed over the LED over time
wire [31:0] blink_pattern = 32'b101010001110111011100010101;
// increment the blink_counter every clock
always @(posedge CLK) begin
blink_counter <= blink_counter + 1;
end
// light up the LED according to the pattern
assign LED = blink_pattern[blink_counter[25:21]];
endmodule