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39 lines
784 B
Plaintext
39 lines
784 B
Plaintext
#-- Lattice, Inc.
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#-- Project file C:\lscc\iCEcube2.2017.01\sbt_backend\Projects\template\template_lse.prj
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#device
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-a SBTiCE40
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-d iCE40LP8K
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-t CM81
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#constraint file
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-sdc "constraints/clk.sdc"
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#options
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-optimization_goal Area
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-twr_paths 3
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-bram_utilization 100.00
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-ramstyle Auto
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-romstyle Auto
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-use_carry_chain 1
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-carry_chain_length 0
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-resource_sharing 1
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-propagate_constants 1
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-remove_duplicate_regs 1
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-max_fanout 10000
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-fsm_encoding_style Auto
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-use_io_insertion 1
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-use_io_reg auto
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-resolve_mixed_drivers 0
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-RWCheckOnRam 0
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-fix_gated_clocks 1
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-loop_limit 1950
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-ver "verilog/TinyFPGA_B.v"
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-p "C:/lscc/iCEcube2.2017.01/sbt_backend/Projects/template"
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#set result format/file last
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-output_edif template_Implmnt/template.edf
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#set log file
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-logfile "template_Implmnt/template_lse.log"
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