first TinyFPGA BX commit after forking from B-series

This commit is contained in:
Luke Valenty
2018-03-30 16:01:43 -07:00
commit aacb636cf0
54 changed files with 44794 additions and 0 deletions

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*_Implmnt/
stdout.log
synlog.tcl
*~
*.swp
*bak
gerbers/
build/
*.pyc

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# TinyFPGA BX
The TinyFPGA BX board is a tiny FPGA board with low cost per logic element and convenient USB bitstream programming capability. It measures just 18mm x 36mm and is a perfect fit for breadboards. The heart of the BX board is a iCE40LP8K-CM81 FPGA from Lattice. For full details on the ICE40 series of FPGAs you can read the [ICE40 Family Handbook](http://www.latticesemi.com/~/media/LatticeSemi/Documents/Handbooks/iCE40FamilyHandbook.pdf).
## Specifications
- Height: 1.4 inches, width: 0.7 inches
- Programming interface: USB 2.0 full-speed (12 mbit/sec)
- ICE40LP8K FPGA
- 7,680 four-input look-up-tables
- 128 KBit block RAM
- Phase Locked Loop
- 41 user IO pins
- 8 MBit of SPI Flash
- Onboard 3.3 V (300 mA) and 1.2 V (150 mA) LDO regulators
- Low-Power 16 MHz MEMs Oscillator
- 1.3 mA power when active
- 50 ppm stability.
## Building your own TinyFPGA BX Board
It is possible to build the TinyFPGA BX boards by hand in a home lab. However, it uses tiny 0402 surface mount capacitors and resistors and the iCE40 FPGAs used are in a 81 ball BGA package with 0.4mm pitch between the balls. It is a challenging undertaking and will most likely result in some bad assembled boards along with the good. I have used the following with success to hand assemble the prototype boards:
+ Parts for the [TinyFPGA BX](https://octopart.com/bom-tool/ALrZVouf)
+ [Lead-Free Solder Paste](https://www.amazon.com/gp/product/B00HKK6XHC)
+ [Stainless Steel Solder Paste Squeegee](http://dirtypcbs.com/store/details/14/solder-paste-squeegee)
+ [TinyFPGA BX Solder Paste Stencil](https://www.oshstencils.com)
+ You'll need to generate the gerber files and upload the solder paste layer. If you plan on using solder paste for the FPGA chip, you will want the stainless steel stencil, I do not believe the polymide will work with the fine pitch BGA package. I have found that fine-pitch BGA packages are easier to assemble with only flux and no paste for prototypes.
+ [TinyFPGA BX PCBs](https://oshpark.com/shared_projects/uMrRTfyL)
+ OSH Park does a very nice job with these boards on their 4-layer process.
+ [Precision Tweezers](https://www.amazon.com/Precision-Anti-static-Marrywindix-Electronics-Jewelry-making/dp/B00DVIEJ14) for placing parts on the board
+ Some sort of magnifying tool for placing parts ([magnifying glasses](https://www.amazon.com/dp/B01H8808H6), [magnifying lamp](https://www.amazon.com/Brightech-LightView-SuperBright-Magnifier-Adjustable/dp/B00UW2IRJ2), microscope)
+ [Reflow Oven](http://www.whizoo.com/)
+ This is the kit I use to reflow my prototypes. You may also be able to use a good hot-plate or hot-air tool.
+ [Lattice FPGA Programmer](https://www.ebay.com/sch/i.html?_productid=533163279)
+ You will need this to load the bootloader onto the SPI Flash. Once the bootloader is installed you can use the Python-based programmer application to program the board over USB.
## Buy TinyFPGA BX Boards
If you don't want to go through the hassle of ordering parts, tools, and supplies and assembling the boards yourself you can order professionally assembled and tested boards from [Crowd Supply](https://www.crowdsupply.com/tinyfpga/tinyfpga-bx). These boards are not hobbyist-made, they are fabricated and assembled in a professional PCB fab that manufactures and assembles many other consumer, industrial and military electronics. They go through an automated testing and programming process to ensure the board is healthy and ready to program over USB. When the Crowd Supply campaign ends and all the backers orders are shipped the boards will become available on Tindie and the TinyFPGA Store.
## Project Directory Structure
### board
This contains a [KiCad](http://kicad-pcb.org/) project with the schematic and layout of the B-series boards. The board is designed with 4/4mil track size/spacing and 0.2mm hole size. BOM list for the BX board is available here as well.
### icecube2_template
This is a template iCEcube2 project for developing your own designs to program onto the board. It takes care of pin and clock constraints. Just edit the TinyFPGA_BX.v file to add your designs module(s).
### icestorm_template
This is a template IceStorm project for developing your own designs to program onto the board. It takes care of pin and clock constraints. Just edit the TinyFPGA_BX.v file to add your designs module(s). Use `make` to build your project.
## Project Log
For more information on the development and production of the B-Series please read and follow the [TinyFPGA B-Series Project Page](https://hackaday.io/project/26848-tinyfpga-b-series) at hackaday.io.
## License
The TinyFPGA BX project is an open source project licensed under CERN Open Hardware Licence v1.2. Please see the included LICENSE file for details. If you do wish to distribute boards derived from this open source hardware project then you must also release the source files for the boards under CERN Open Hardware Licence v1.2. You are free to do this, but please improve upon the original design and provide a tangible benefit for users of the board.

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EESchema-LIBRARY Version 2.3
#encoding utf-8
#
# +1V2
#
DEF +1V2 #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -150 50 H I C CNN
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F3 "" 0 0 50 H I C CNN
DRAW
P 2 0 1 0 -30 50 0 100 N
P 2 0 1 0 0 0 0 100 N
P 2 0 1 0 0 100 30 50 N
X +1V2 1 0 0 0 U 50 50 1 1 W N
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# +3V3
#
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F0 "#PWR" 0 -150 50 H I C CNN
F1 "+3V3" 0 140 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
ALIAS +3.3V
DRAW
P 2 0 1 0 -30 50 0 100 N
P 2 0 1 0 0 0 0 100 N
P 2 0 1 0 0 100 30 50 N
X +3V3 1 0 0 0 U 50 50 1 1 W N
ENDDRAW
ENDDEF
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# +5V
#
DEF +5V #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -150 50 H I C CNN
F1 "+5V" 0 140 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
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P 2 0 1 0 0 0 0 100 N
P 2 0 1 0 0 100 30 50 N
X +5V 1 0 0 0 U 50 50 1 1 W N
ENDDRAW
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# AT25SF041-SSHD-B
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DEF AT25SF041-SSHD-B U 0 40 Y Y 1 L N
F0 "U" 150 250 60 H V R CNN
F1 "AT25SF041-SSHD-B" 150 150 60 H V R CNN
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F3 "" 0 0 60 H I C CNN
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S 200 400 1200 -700 1 1 12 N
X !CS 1 1400 -300 200 L 50 50 1 1 B
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X VCC 8 700 600 200 D 50 50 1 1 B
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# C
#
DEF C C 0 10 N Y 1 F N
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C_*
$ENDFPLIST
DRAW
P 2 0 1 20 -80 -30 80 -30 N
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ENDDRAW
ENDDEF
#
# C_Small
#
DEF C_Small C 0 10 N N 1 F N
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$ENDFPLIST
DRAW
P 2 0 1 13 -60 -20 60 -20 N
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ENDDRAW
ENDDEF
#
# Conn_01x14
#
DEF Conn_01x14 J 0 40 Y N 1 F N
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F1 "Conn_01x14" 0 -800 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
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Connector*:*1x??x*mm*
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$ENDFPLIST
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X Pin_10 10 -200 -300 150 R 50 50 1 1 P
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X Pin_13 13 -200 -600 150 R 50 50 1 1 P
X Pin_14 14 -200 -700 150 R 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Conn_02x03_Odd_Even
#
DEF Conn_02x03_Odd_Even J 0 40 Y N 1 F N
F0 "J" 50 200 50 H V C CNN
F1 "Conn_02x03_Odd_Even" 50 -200 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
Connector*:*2x??x*mm*
Connector*:*2x???Pitch*
Pin_Header_Straight_2X*
Pin_Header_Angled_2X*
Socket_Strip_Straight_2X*
Socket_Strip_Angled_2X*
$ENDFPLIST
DRAW
S -50 -95 0 -105 1 1 6 N
S -50 5 0 -5 1 1 6 N
S -50 105 0 95 1 1 6 N
S -50 150 150 -150 1 1 10 f
S 150 -95 100 -105 1 1 6 N
S 150 5 100 -5 1 1 6 N
S 150 105 100 95 1 1 6 N
X Pin_1 1 -200 100 150 R 50 50 1 1 P
X Pin_2 2 300 100 150 L 50 50 1 1 P
X Pin_3 3 -200 0 150 R 50 50 1 1 P
X Pin_4 4 300 0 150 L 50 50 1 1 P
X Pin_5 5 -200 -100 150 R 50 50 1 1 P
X Pin_6 6 300 -100 150 L 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Conn_02x08_Odd_Even
#
DEF Conn_02x08_Odd_Even J 0 40 Y N 1 F N
F0 "J" 50 400 50 H V C CNN
F1 "Conn_02x08_Odd_Even" 50 -500 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
Connector*:*2x??x*mm*
Connector*:*2x???Pitch*
Pin_Header_Straight_2X*
Pin_Header_Angled_2X*
Socket_Strip_Straight_2X*
Socket_Strip_Angled_2X*
$ENDFPLIST
DRAW
S -50 -395 0 -405 1 1 6 N
S -50 -295 0 -305 1 1 6 N
S -50 -195 0 -205 1 1 6 N
S -50 -95 0 -105 1 1 6 N
S -50 5 0 -5 1 1 6 N
S -50 105 0 95 1 1 6 N
S -50 205 0 195 1 1 6 N
S -50 305 0 295 1 1 6 N
S -50 350 150 -450 1 1 10 f
S 150 -395 100 -405 1 1 6 N
S 150 -295 100 -305 1 1 6 N
S 150 -195 100 -205 1 1 6 N
S 150 -95 100 -105 1 1 6 N
S 150 5 100 -5 1 1 6 N
S 150 105 100 95 1 1 6 N
S 150 205 100 195 1 1 6 N
S 150 305 100 295 1 1 6 N
X Pin_1 1 -200 300 150 R 50 50 1 1 P
X Pin_2 2 300 300 150 L 50 50 1 1 P
X Pin_3 3 -200 200 150 R 50 50 1 1 P
X Pin_4 4 300 200 150 L 50 50 1 1 P
X Pin_5 5 -200 100 150 R 50 50 1 1 P
X Pin_6 6 300 100 150 L 50 50 1 1 P
X Pin_7 7 -200 0 150 R 50 50 1 1 P
X Pin_8 8 300 0 150 L 50 50 1 1 P
X Pin_9 9 -200 -100 150 R 50 50 1 1 P
X Pin_10 10 300 -100 150 L 50 50 1 1 P
X Pin_11 11 -200 -200 150 R 50 50 1 1 P
X Pin_12 12 300 -200 150 L 50 50 1 1 P
X Pin_13 13 -200 -300 150 R 50 50 1 1 P
X Pin_14 14 300 -300 150 L 50 50 1 1 P
X Pin_15 15 -200 -400 150 R 50 50 1 1 P
X Pin_16 16 300 -400 150 L 50 50 1 1 P
ENDDRAW
ENDDEF
#
# DSC6001CI2A-016.0000T
#
DEF DSC6001CI2A-016.0000T U 0 40 Y Y 1 L N
F0 "U" 150 250 60 H V R CNN
F1 "DSC6001CI2A-016.0000T" 150 150 60 H V R CNN
F2 "" 0 0 60 H I C CNN
F3 "" 0 0 60 H I C CNN
DRAW
S 200 400 1000 -400 1 1 12 N
X OE 1 0 0 200 R 50 50 1 1 B
X GND 2 600 -600 200 U 50 50 1 1 B
X OUT 3 1200 0 200 L 50 50 1 1 B
X VDD 4 600 600 200 D 50 50 1 1 B
ENDDRAW
ENDDEF
#
# Ferrite_Bead_Small
#
DEF Ferrite_Bead_Small L 0 0 N Y 1 F N
F0 "L" 75 50 50 H V L CNN
F1 "Ferrite_Bead_Small" 75 -50 50 H V L CNN
F2 "" -70 0 50 V I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
Inductor_*
L_*
*Ferrite*
$ENDFPLIST
DRAW
P 2 0 1 0 0 -50 0 -31 N
P 2 0 1 0 0 35 0 51 N
P 5 0 1 0 -72 11 -44 59 72 -8 44 -56 -72 11 N
X ~ 1 0 100 50 D 50 50 1 1 P
X ~ 2 0 -100 50 U 50 50 1 1 P
ENDDRAW
ENDDEF
#
# GND
#
DEF GND #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -250 50 H I C CNN
F1 "GND" 0 -150 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N
X GND 1 0 0 0 D 50 50 1 1 W N
ENDDRAW
ENDDEF
#
# LED_Small
#
DEF LED_Small D 0 10 N N 1 F N
F0 "D" -50 125 50 H V L CNN
F1 "LED_Small" -175 -100 50 H V L CNN
F2 "" 0 0 50 V I C CNN
F3 "" 0 0 50 V I C CNN
$FPLIST
LED-*
LED_*
$ENDFPLIST
DRAW
P 2 0 1 0 -30 -40 -30 40 N
P 2 0 1 0 40 0 -30 0 N
P 4 0 1 0 30 -40 -30 0 30 40 30 -40 N
P 5 0 1 0 0 30 -20 50 -10 50 -20 50 -20 40 N
P 5 0 1 0 20 50 0 70 10 70 0 70 0 60 N
X K 1 -100 0 70 R 50 50 1 1 P
X A 2 100 0 70 L 50 50 1 1 P
ENDDRAW
ENDDEF
#
# MIC5365-1.2YC5-TR
#
DEF MIC5365-1.2YC5-TR U 0 40 Y Y 1 L N
F0 "U" 200 250 60 H V L CNN
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F2 "" 0 0 60 H I C CNN
F3 "" 0 0 60 H I C CNN
DRAW
S 200 100 1000 -500 1 1 12 N
X VIN 1 0 0 200 R 50 50 1 1 B
X GND 2 600 -700 200 U 50 50 1 1 B
X EN 3 0 -100 200 R 50 50 1 1 B
X NC 4 1200 0 200 L 50 50 1 1 B
X VOUT 5 1200 -100 200 L 50 50 1 1 B
ENDDRAW
ENDDEF
#
# MIC5504-3.3YM5-TR
#
DEF MIC5504-3.3YM5-TR U 0 40 Y Y 1 L N
F0 "U" 200 250 60 H V L CNN
F1 "MIC5504-3.3YM5-TR" 200 150 60 H V L CNN
F2 "" 0 0 60 H I C CNN
F3 "" 0 0 60 H I C CNN
DRAW
S 200 100 1000 -500 1 1 12 N
X VIN 1 0 0 200 R 50 50 1 1 B
X GND 2 600 -700 200 U 50 50 1 1 B
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#
# R
#
DEF R R 0 0 N Y 1 F N
F0 "R" 80 0 50 V V C CNN
F1 "R" 0 0 50 V V C CNN
F2 "" -70 0 50 V I C CNN
F3 "" 0 0 50 H I C CNN
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R_*
R_*
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S -40 -100 40 100 0 1 10 N
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ENDDRAW
ENDDEF
#
# R_Small
#
DEF R_Small R 0 10 N N 1 F N
F0 "R" 30 20 50 H V L CNN
F1 "R_Small" 30 -40 50 H V L CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
R_*
$ENDFPLIST
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S -30 70 30 -70 0 1 8 N
X ~ 1 0 100 30 D 50 50 1 1 P
X ~ 2 0 -100 30 U 50 50 1 1 P
ENDDRAW
ENDDEF
#
# SW_Push
#
DEF SW_Push SW 0 40 N N 1 F N
F0 "SW" 50 100 50 H V L CNN
F1 "SW_Push" 0 -60 50 H V C CNN
F2 "" 0 200 50 H I C CNN
F3 "" 0 200 50 H I C CNN
DRAW
C -80 0 20 0 1 0 N
C 80 0 20 0 1 0 N
P 2 0 1 0 0 50 0 120 N
P 2 0 1 0 100 50 -100 50 N
X 1 1 -200 0 100 R 50 50 0 1 P
X 2 2 200 0 100 L 50 50 0 1 P
ENDDRAW
ENDDEF
#
# TEST
#
DEF TEST TP 0 40 N N 1 F N
F0 "TP" 0 300 50 H V C BNN
F1 "TEST" 0 250 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
P 6 0 1 0 0 200 -50 150 0 100 50 150 0 200 0 200 N
X ~ 1 0 0 100 U 50 50 1 1 P
ENDDRAW
ENDDEF
#
# USB_OTG
#
DEF USB_OTG J 0 40 Y Y 1 F N
F0 "J" -200 450 50 H V L CNN
F1 "USB_OTG" -200 350 50 H V L CNN
F2 "" 150 -50 50 H I C CNN
F3 "" 150 -50 50 H I C CNN
$FPLIST
USB*
$ENDFPLIST
DRAW
C -150 85 25 0 1 10 F
C -25 135 15 0 1 10 F
S -200 -300 200 300 0 1 10 f
S -5 -300 5 -270 0 1 0 N
S 10 50 -20 20 0 1 10 F
S 200 -205 170 -195 0 1 0 N
S 200 -105 170 -95 0 1 0 N
S 200 -5 170 5 0 1 0 N
S 200 195 170 205 0 1 0 N
P 2 0 1 10 -75 85 25 85 N
P 4 0 1 10 -125 85 -100 85 -50 135 -25 135 N
P 4 0 1 10 -100 85 -75 85 -50 35 0 35 N
P 4 0 1 10 25 110 25 60 75 85 25 110 F
P 5 0 1 0 -170 220 -70 220 -80 190 -160 190 -170 220 F
P 9 0 1 0 -185 230 -185 220 -175 190 -175 180 -65 180 -65 190 -55 220 -55 230 -185 230 N
X VBUS 1 300 200 100 L 50 50 1 1 W
X D- 2 300 -100 100 L 50 50 1 1 P
X D+ 3 300 0 100 L 50 50 1 1 P
X ID 4 300 -200 100 L 50 50 1 1 P
X GND 5 0 -400 100 U 50 50 1 1 W
X Shield 6 -100 -400 100 U 50 50 1 1 P
ENDDRAW
ENDDEF
#
# iCE40-LP8K-CM81
#
DEF iCE40-LP8K-CM81 U 0 40 Y Y 8 L N
F0 "U" 200 250 60 H V L CNN
F1 "iCE40-LP8K-CM81" 200 150 60 H V L CNN
F2 "" 0 0 60 H I C CNN
F3 "" 0 0 60 H I C CNN
DRAW
S 200 100 1000 -1000 1 1 12 N
X IOB_103_CBSEL0 G5 0 -300 200 R 50 50 1 1 B
X IOB_104_CBSEL1 H5 0 -600 200 R 50 50 1 1 B
X CDONE E6 0 -200 200 R 50 50 1 1 B
X IOB_105_SDO G6 0 -400 200 R 50 50 1 1 B
X CRESET_B H6 0 -700 200 R 50 50 1 1 B
X VPP_FAST C7 0 0 200 R 50 50 1 1 B
X IOB_107_SCK G7 0 -500 200 R 50 50 1 1 B
X IOB_106_SDI H7 0 -800 200 R 50 50 1 1 B
X VPP_2V5 C8 0 -100 200 R 50 50 1 1 B
X VCC_SPI H8 0 -900 200 R 50 50 1 1 B
S 200 100 500 -400 2 1 12 N
X GND F4 0 0 200 R 50 50 2 1 B
X GND F5 0 -100 200 R 50 50 2 1 B
X GND F6 0 -200 200 R 50 50 2 1 B
X GND F9 0 -300 200 R 50 50 2 1 B
S 200 100 900 -800 3 1 12 N
X IOB_54 H1 0 -200 200 R 50 50 3 1 B
X IOB_55 J1 0 -400 200 R 50 50 3 1 B
X IOB_56 J2 0 -500 200 R 50 50 3 1 B
X IOB_57 J3 0 -600 200 R 50 50 3 1 B
X IOB_81_GBIN5 G4 0 -100 200 R 50 50 3 1 B
X IOB_82_GBIN4 H4 0 -300 200 R 50 50 3 1 B
X IOB_70 J4 0 -700 200 R 50 50 3 1 B
X IOB_108_SS F7 0 0 200 R 50 50 3 1 B
S 200 100 1000 -1800 4 1 12 N
X IOL_3A B1 0 0 200 R 50 50 4 1 B
X IOL_3B C1 0 -200 200 R 50 50 4 1 B
X IOL_10A D1 0 -500 200 R 50 50 4 1 B
X IOL_10B E1 0 -800 200 R 50 50 4 1 B
X IOL_22A F1 0 -1200 200 R 50 50 4 1 B
X IOL_24B G1 0 -1400 200 R 50 50 4 1 B
X IOL_2B B2 0 -100 200 R 50 50 4 1 B
X IOL_2A C2 0 -300 200 R 50 50 4 1 B
X IOL_7A D2 0 -600 200 R 50 50 4 1 B
X IOL_13A E2 0 -900 200 R 50 50 4 1 B
X IOL_26A G2 0 -1500 200 R 50 50 4 1 B
X IOL_26B H2 0 -1700 200 R 50 50 4 1 B
X IOL_7B C3 0 -400 200 R 50 50 4 1 B
X IOL_13B_GBIN7 D3 0 -700 200 R 50 50 4 1 B
X IOL_14A_GBIN6 E3 0 -1000 200 R 50 50 4 1 B
X IOL_22B F3 0 -1300 200 R 50 50 4 1 B
X IOL_24A G3 0 -1600 200 R 50 50 4 1 B
X IOL_14B E4 0 -1100 200 R 50 50 4 1 B
S 200 100 1000 -1500 5 1 12 N
X IOR_115 D6 0 -300 200 R 50 50 5 1 B
X IOR_117 D7 0 -400 200 R 50 50 5 1 B
X IOR_118 E7 0 -700 200 R 50 50 5 1 B
X IOR_141_GBIN2 D8 0 -500 200 R 50 50 5 1 B
X IOR_140_GBIN3 E8 0 -800 200 R 50 50 5 1 B
X IOR_113 F8 0 -900 200 R 50 50 5 1 B
X IOR_114 G8 0 -1000 200 R 50 50 5 1 B
X IOR_109 J8 0 -1300 200 R 50 50 5 1 B
X IOR_116 A9 0 0 200 R 50 50 5 1 B
X IOR_120 B9 0 -100 200 R 50 50 5 1 B
X IOR_148 C9 0 -200 200 R 50 50 5 1 B
X IOR_119 D9 0 -600 200 R 50 50 5 1 B
X IOR_112 G9 0 -1100 200 R 50 50 5 1 B
X IOR_111 H9 0 -1200 200 R 50 50 5 1 B
X IOR_110 J9 0 -1400 200 R 50 50 5 1 B
S 200 100 1000 -1700 6 1 12 N
X IOT_224 A1 0 0 200 R 50 50 6 1 B
X IOT_221 A2 0 -100 200 R 50 50 6 1 B
X IOT_217 A3 0 -200 200 R 50 50 6 1 B
X IOT_218 B3 0 -700 200 R 50 50 6 1 B
X IOT_208 A4 0 -300 200 R 50 50 6 1 B
X IOT_211 B4 0 -800 200 R 50 50 6 1 B
X IOT_198_GBIN0 C4 0 -1300 200 R 50 50 6 1 B
X IOT_188 B5 0 -900 200 R 50 50 6 1 B
X IOT_197_GBIN1 C5 0 -1400 200 R 50 50 6 1 B
X IOT_212 D5 0 -1500 200 R 50 50 6 1 B
X IOT_214 E5 0 -1600 200 R 50 50 6 1 B
X IOT_185 A6 0 -400 200 R 50 50 6 1 B
X IOT_183 B6 0 -1000 200 R 50 50 6 1 B
X IOT_177 A7 0 -500 200 R 50 50 6 1 B
X IOT_180 B7 0 -1100 200 R 50 50 6 1 B
X IOT_174 A8 0 -600 200 R 50 50 6 1 B
X IOT_170 B8 0 -1200 200 R 50 50 6 1 B
S 200 100 700 -200 7 1 12 N
X GNDPLL0 J6 0 0 200 R 50 50 7 1 B
X VCCPLL0 J7 0 -100 200 R 50 50 7 1 B
S 200 100 700 -700 8 1 12 N
X VCC F2 0 -400 200 R 50 50 8 1 B
X VCCIO_3 H3 0 -500 200 R 50 50 8 1 B
X VCC D4 0 -200 200 R 50 50 8 1 B
X VCCIO_0 A5 0 0 200 R 50 50 8 1 B
X VCCIO_2 J5 0 -600 200 R 50 50 8 1 B
X VCCIO_1 C6 0 -100 200 R 50 50 8 1 B
X VCC E9 0 -300 200 R 50 50 8 1 B
ENDDRAW
ENDDEF
#
#End Library

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EESchema-LIBRARY Version 2.3
#encoding utf-8
#
#End Library

4040
board/TinyFPGA-BX.kicad_pcb Normal file
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board/TinyFPGA-BX.net Normal file
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(export (version D)
(design
(source C:/Users/lvale/Documents/TinyFPGA/repos/TinyFPGA-BX/board/TinyFPGA-BX.sch)
(date "3/27/2018 7:10:47 PM")
(tool "Eeschema 4.0.7")
(sheet (number 1) (name /) (tstamps /)
(title_block
(title "TinyFPGA Bx")
(company TinyFPGA)
(rev v1.1)
(date)
(source TinyFPGA-BX.sch)
(comment (number 1) (value ""))
(comment (number 2) (value ""))
(comment (number 3) (value ""))
(comment (number 4) (value "")))))
(components
(comp (ref U1)
(value iCE40-LP8K-CM81)
(footprint tinyfpga:CM81)
(libsource (lib tinyfpga) (part iCE40-LP8K-CM81))
(sheetpath (names /) (tstamps /))
(tstamp 591007FD))
(comp (ref J1)
(value CONN_01X14)
(footprint Pin_Headers:Pin_Header_Straight_1x14_Pitch2.54mm)
(libsource (lib conn) (part Conn_01x14))
(sheetpath (names /) (tstamps /))
(tstamp 591076F8))
(comp (ref J2)
(value CONN_01X14)
(footprint Pin_Headers:Pin_Header_Straight_1x14_Pitch2.54mm)
(libsource (lib conn) (part Conn_01x14))
(sheetpath (names /) (tstamps /))
(tstamp 5910778F))
(comp (ref J3)
(value USB_OTG)
(footprint Connectors:USB_Micro-B)
(libsource (lib conn) (part USB_OTG))
(sheetpath (names /) (tstamps /))
(tstamp 5918C75D))
(comp (ref SW1)
(value SW_Push)
(footprint tinyfpga:PTS_810_SMT_Switch)
(libsource (lib switches) (part SW_Push))
(sheetpath (names /) (tstamps /))
(tstamp 5918CB81))
(comp (ref U4)
(value MIC5365-1.2YC5-TR)
(footprint tinyfpga:SC-70-C5)
(libsource (lib tinyfpga) (part MIC5365-1.2YC5-TR))
(sheetpath (names /) (tstamps /))
(tstamp 591A9EDF))
(comp (ref U2)
(value MIC5504-3.3YM5-TR)
(footprint tinyfpga:SC-70-C5)
(libsource (lib tinyfpga) (part MIC5504-3.3YM5-TR))
(sheetpath (names /) (tstamps /))
(tstamp 591A9F5A))
(comp (ref U3)
(value DSC6001CI2A-016.0000T)
(footprint tinyfpga:CDFN3225-4LD-PL-1)
(libsource (lib tinyfpga) (part DSC6001CI2A-016.0000T))
(sheetpath (names /) (tstamps /))
(tstamp 591A9FD7))
(comp (ref U5)
(value AT25SF081-SSHD-B)
(footprint Housings_SOIC:SOIC-8-1EP_3.9x4.9mm_Pitch1.27mm)
(libsource (lib tinyfpga) (part AT25SF041-SSHD-B))
(sheetpath (names /) (tstamps /))
(tstamp 591BDF5F))
(comp (ref C2)
(value 1uF)
(footprint Capacitors_SMD:C_0402_NoSilk)
(libsource (lib device) (part C))
(sheetpath (names /) (tstamps /))
(tstamp 591BF1F2))
(comp (ref C3)
(value 1uF)
(footprint Capacitors_SMD:C_0402_NoSilk)
(libsource (lib device) (part C))
(sheetpath (names /) (tstamps /))
(tstamp 591BF26D))
(comp (ref C1)
(value 1uF)
(footprint Capacitors_SMD:C_0402_NoSilk)
(libsource (lib device) (part C))
(sheetpath (names /) (tstamps /))
(tstamp 591C09B3))
(comp (ref C4)
(value 1uF)
(footprint Capacitors_SMD:C_0402_NoSilk)
(libsource (lib device) (part C))
(sheetpath (names /) (tstamps /))
(tstamp 591C0A32))
(comp (ref L1)
(value Bead)
(footprint Inductors_SMD:L_0603)
(libsource (lib device) (part Ferrite_Bead_Small))
(sheetpath (names /) (tstamps /))
(tstamp 591C2A75))
(comp (ref R2)
(value 68)
(footprint Resistors_SMD:R_0402_NoSilk)
(libsource (lib device) (part R))
(sheetpath (names /) (tstamps /))
(tstamp 591D2293))
(comp (ref R3)
(value 68)
(footprint Resistors_SMD:R_0402_NoSilk)
(libsource (lib device) (part R))
(sheetpath (names /) (tstamps /))
(tstamp 591D2392))
(comp (ref R1)
(value 1.5k)
(footprint Resistors_SMD:R_0402_NoSilk)
(libsource (lib device) (part R))
(sheetpath (names /) (tstamps /))
(tstamp 591D2427))
(comp (ref C5)
(value 100nF)
(footprint Capacitors_SMD:C_0402_NoSilk)
(libsource (lib device) (part C))
(sheetpath (names /) (tstamps /))
(tstamp 591E10BF))
(comp (ref C8)
(value 100nF)
(footprint Capacitors_SMD:C_0402_NoSilk)
(libsource (lib device) (part C))
(sheetpath (names /) (tstamps /))
(tstamp 591E1ADB))
(comp (ref C7)
(value 100nF)
(footprint Capacitors_SMD:C_0402_NoSilk)
(libsource (lib device) (part C))
(sheetpath (names /) (tstamps /))
(tstamp 591E2ADF))
(comp (ref C6)
(value 10uF)
(footprint Capacitors_SMD:C_0603)
(libsource (lib device) (part C))
(sheetpath (names /) (tstamps /))
(tstamp 591E2B9D))
(comp (ref R4)
(value 100)
(footprint Resistors_SMD:R_0402_NoSilk)
(libsource (lib device) (part R))
(sheetpath (names /) (tstamps /))
(tstamp 591E2BF1))
(comp (ref C9)
(value 100nF)
(footprint Capacitors_SMD:C_0402_NoSilk)
(libsource (lib device) (part C_Small))
(sheetpath (names /) (tstamps /))
(tstamp 591E9D9B))
(comp (ref C10)
(value 100nF)
(footprint Capacitors_SMD:C_0402_NoSilk)
(libsource (lib device) (part C_Small))
(sheetpath (names /) (tstamps /))
(tstamp 591E9E78))
(comp (ref C11)
(value 100nF)
(footprint Capacitors_SMD:C_0402_NoSilk)
(libsource (lib device) (part C_Small))
(sheetpath (names /) (tstamps /))
(tstamp 591E9EF1))
(comp (ref C12)
(value 10nF)
(footprint Capacitors_SMD:C_0402_NoSilk)
(libsource (lib device) (part C_Small))
(sheetpath (names /) (tstamps /))
(tstamp 591E9FF1))
(comp (ref C13)
(value 10nF)
(footprint Capacitors_SMD:C_0402_NoSilk)
(libsource (lib device) (part C_Small))
(sheetpath (names /) (tstamps /))
(tstamp 591EA15E))
(comp (ref C14)
(value 10nF)
(footprint Capacitors_SMD:C_0402_NoSilk)
(libsource (lib device) (part C_Small))
(sheetpath (names /) (tstamps /))
(tstamp 591EA1D8))
(comp (ref C15)
(value 10nF)
(footprint Capacitors_SMD:C_0402_NoSilk)
(libsource (lib device) (part C_Small))
(sheetpath (names /) (tstamps /))
(tstamp 591EA257))
(comp (ref R5)
(value 10k)
(footprint Resistors_SMD:R_0402_NoSilk)
(libsource (lib device) (part R))
(sheetpath (names /) (tstamps /))
(tstamp 591EBB96))
(comp (ref C16)
(value 100nF)
(footprint Capacitors_SMD:C_0402_NoSilk)
(libsource (lib device) (part C_Small))
(sheetpath (names /) (tstamps /))
(tstamp 591EA04F))
(comp (ref R6)
(value R)
(footprint Resistors_SMD:R_0402)
(libsource (lib device) (part R))
(sheetpath (names /) (tstamps /))
(tstamp 592015DC))
(comp (ref C17)
(value 10uF)
(footprint Capacitors_SMD:C_0603)
(libsource (lib device) (part C))
(sheetpath (names /) (tstamps /))
(tstamp 592061E2))
(comp (ref R7)
(value 10k)
(footprint Resistors_SMD:R_0402_NoSilk)
(libsource (lib device) (part R))
(sheetpath (names /) (tstamps /))
(tstamp 5922D14B))
(comp (ref TP1)
(value TEST)
(footprint Measurement_Points:Measurement_Point_Round-SMD-Pad_Small)
(libsource (lib device) (part TEST))
(sheetpath (names /) (tstamps /))
(tstamp 5922E3E0))
(comp (ref TP2)
(value TEST)
(footprint Measurement_Points:Measurement_Point_Round-SMD-Pad_Small)
(libsource (lib device) (part TEST))
(sheetpath (names /) (tstamps /))
(tstamp 5923D3AB))
(comp (ref D1)
(value LED_Small)
(footprint LEDs:LED_0603)
(libsource (lib device) (part LED_Small))
(sheetpath (names /) (tstamps /))
(tstamp 5A3A94CB))
(comp (ref D2)
(value LED_Small)
(footprint LEDs:LED_0603)
(libsource (lib device) (part LED_Small))
(sheetpath (names /) (tstamps /))
(tstamp 5A3A9582))
(comp (ref R8)
(value 270)
(footprint Resistors_SMD:R_0402_NoSilk)
(libsource (lib device) (part R_Small))
(sheetpath (names /) (tstamps /))
(tstamp 5A3A95FA))
(comp (ref R9)
(value 270)
(footprint Resistors_SMD:R_0402_NoSilk)
(libsource (lib device) (part R_Small))
(sheetpath (names /) (tstamps /))
(tstamp 5A3A96BD))
(comp (ref TP3)
(value TEST)
(footprint Measurement_Points:Measurement_Point_Round-SMD-Pad_Small)
(libsource (lib device) (part TEST))
(sheetpath (names /) (tstamps /))
(tstamp 5A3B49B1))
(comp (ref J5)
(value Conn_02x03_Odd_Even)
(footprint Pin_Headers:Pin_Header_Straight_2x03_Pitch2.54mm_SMD)
(libsource (lib conn) (part Conn_02x03_Odd_Even))
(sheetpath (names /) (tstamps /))
(tstamp 5A3BFD22))
(comp (ref J4)
(value Conn_02x08_Odd_Even)
(footprint Pin_Headers:Pin_Header_Straight_2x08_Pitch2.54mm_SMD)
(libsource (lib conn) (part Conn_02x08_Odd_Even))
(sheetpath (names /) (tstamps /))
(tstamp 5A9C6A1C))
(comp (ref R10)
(value 10k)
(footprint Resistors_SMD:R_0402_NoSilk)
(libsource (lib device) (part R))
(sheetpath (names /) (tstamps /))
(tstamp 5ABB1098)))
(libparts
(libpart (lib tinyfpga) (part AT25SF041-SSHD-B)
(fields
(field (name Reference) U)
(field (name Value) AT25SF041-SSHD-B))
(pins
(pin (num 1) (name !CS) (type BiDi))
(pin (num 2) (name SO) (type BiDi))
(pin (num 3) (name !WP) (type BiDi))
(pin (num 4) (name GND) (type BiDi))
(pin (num 5) (name SI) (type BiDi))
(pin (num 6) (name SCK) (type BiDi))
(pin (num 7) (name !HOLD) (type BiDi))
(pin (num 8) (name VCC) (type BiDi))))
(libpart (lib device) (part C)
(description "Unpolarized capacitor")
(footprints
(fp C_*))
(fields
(field (name Reference) C)
(field (name Value) C))
(pins
(pin (num 1) (name ~) (type passive))
(pin (num 2) (name ~) (type passive))))
(libpart (lib device) (part C_Small)
(description "Unpolarized capacitor")
(footprints
(fp C_*))
(fields
(field (name Reference) C)
(field (name Value) C_Small))
(pins
(pin (num 1) (name ~) (type passive))
(pin (num 2) (name ~) (type passive))))
(libpart (lib conn) (part Conn_01x14)
(description "Generic connector, single row, 01x14")
(docs ~)
(footprints
(fp Connector*:*_??x*mm*)
(fp Connector*:*1x??x*mm*)
(fp Pin?Header?Straight?1X*)
(fp Pin?Header?Angled?1X*)
(fp Socket?Strip?Straight?1X*)
(fp Socket?Strip?Angled?1X*))
(fields
(field (name Reference) J)
(field (name Value) Conn_01x14))
(pins
(pin (num 1) (name Pin_1) (type passive))
(pin (num 2) (name Pin_2) (type passive))
(pin (num 3) (name Pin_3) (type passive))
(pin (num 4) (name Pin_4) (type passive))
(pin (num 5) (name Pin_5) (type passive))
(pin (num 6) (name Pin_6) (type passive))
(pin (num 7) (name Pin_7) (type passive))
(pin (num 8) (name Pin_8) (type passive))
(pin (num 9) (name Pin_9) (type passive))
(pin (num 10) (name Pin_10) (type passive))
(pin (num 11) (name Pin_11) (type passive))
(pin (num 12) (name Pin_12) (type passive))
(pin (num 13) (name Pin_13) (type passive))
(pin (num 14) (name Pin_14) (type passive))))
(libpart (lib conn) (part Conn_02x03_Odd_Even)
(description "Generic connector, double row, 02x03, odd/even pin numbering scheme (row 1 odd numbers, row 2 even numbers)")
(docs ~)
(footprints
(fp Connector*:*2x??x*mm*)
(fp Connector*:*2x???Pitch*)
(fp Pin_Header_Straight_2X*)
(fp Pin_Header_Angled_2X*)
(fp Socket_Strip_Straight_2X*)
(fp Socket_Strip_Angled_2X*))
(fields
(field (name Reference) J)
(field (name Value) Conn_02x03_Odd_Even))
(pins
(pin (num 1) (name Pin_1) (type passive))
(pin (num 2) (name Pin_2) (type passive))
(pin (num 3) (name Pin_3) (type passive))
(pin (num 4) (name Pin_4) (type passive))
(pin (num 5) (name Pin_5) (type passive))
(pin (num 6) (name Pin_6) (type passive))))
(libpart (lib conn) (part Conn_02x08_Odd_Even)
(description "Generic connector, double row, 02x08, odd/even pin numbering scheme (row 1 odd numbers, row 2 even numbers)")
(docs ~)
(footprints
(fp Connector*:*2x??x*mm*)
(fp Connector*:*2x???Pitch*)
(fp Pin_Header_Straight_2X*)
(fp Pin_Header_Angled_2X*)
(fp Socket_Strip_Straight_2X*)
(fp Socket_Strip_Angled_2X*))
(fields
(field (name Reference) J)
(field (name Value) Conn_02x08_Odd_Even))
(pins
(pin (num 1) (name Pin_1) (type passive))
(pin (num 2) (name Pin_2) (type passive))
(pin (num 3) (name Pin_3) (type passive))
(pin (num 4) (name Pin_4) (type passive))
(pin (num 5) (name Pin_5) (type passive))
(pin (num 6) (name Pin_6) (type passive))
(pin (num 7) (name Pin_7) (type passive))
(pin (num 8) (name Pin_8) (type passive))
(pin (num 9) (name Pin_9) (type passive))
(pin (num 10) (name Pin_10) (type passive))
(pin (num 11) (name Pin_11) (type passive))
(pin (num 12) (name Pin_12) (type passive))
(pin (num 13) (name Pin_13) (type passive))
(pin (num 14) (name Pin_14) (type passive))
(pin (num 15) (name Pin_15) (type passive))
(pin (num 16) (name Pin_16) (type passive))))
(libpart (lib tinyfpga) (part DSC6001CI2A-016.0000T)
(fields
(field (name Reference) U)
(field (name Value) DSC6001CI2A-016.0000T))
(pins
(pin (num 1) (name OE) (type BiDi))
(pin (num 2) (name GND) (type BiDi))
(pin (num 3) (name OUT) (type BiDi))
(pin (num 4) (name VDD) (type BiDi))))
(libpart (lib device) (part Ferrite_Bead_Small)
(description "Ferrite bead, small symbol")
(footprints
(fp Inductor_*)
(fp L_*)
(fp *Ferrite*))
(fields
(field (name Reference) L)
(field (name Value) Ferrite_Bead_Small))
(pins
(pin (num 1) (name ~) (type passive))
(pin (num 2) (name ~) (type passive))))
(libpart (lib device) (part LED_Small)
(description "LED, small symbol")
(footprints
(fp LED-*)
(fp LED_*))
(fields
(field (name Reference) D)
(field (name Value) LED_Small))
(pins
(pin (num 1) (name K) (type passive))
(pin (num 2) (name A) (type passive))))
(libpart (lib tinyfpga) (part MIC5365-1.2YC5-TR)
(fields
(field (name Reference) U)
(field (name Value) MIC5365-1.2YC5-TR))
(pins
(pin (num 1) (name VIN) (type BiDi))
(pin (num 2) (name GND) (type BiDi))
(pin (num 3) (name EN) (type BiDi))
(pin (num 4) (name NC) (type BiDi))
(pin (num 5) (name VOUT) (type BiDi))))
(libpart (lib tinyfpga) (part MIC5504-3.3YM5-TR)
(fields
(field (name Reference) U)
(field (name Value) MIC5504-3.3YM5-TR))
(pins
(pin (num 1) (name VIN) (type BiDi))
(pin (num 2) (name GND) (type BiDi))
(pin (num 3) (name EN) (type BiDi))
(pin (num 4) (name NC) (type BiDi))
(pin (num 5) (name VOUT) (type BiDi))))
(libpart (lib device) (part R)
(description Resistor)
(footprints
(fp R_*)
(fp R_*))
(fields
(field (name Reference) R)
(field (name Value) R))
(pins
(pin (num 1) (name ~) (type passive))
(pin (num 2) (name ~) (type passive))))
(libpart (lib device) (part R_Small)
(description "Resistor, small symbol")
(footprints
(fp R_*))
(fields
(field (name Reference) R)
(field (name Value) R_Small))
(pins
(pin (num 1) (name ~) (type passive))
(pin (num 2) (name ~) (type passive))))
(libpart (lib switches) (part SW_Push)
(description "Push button switch, generic, two pins")
(fields
(field (name Reference) SW)
(field (name Value) SW_Push))
(pins
(pin (num 1) (name 1) (type passive))
(pin (num 2) (name 2) (type passive))))
(libpart (lib device) (part TEST)
(description "Testpoint, connection for test equipment")
(fields
(field (name Reference) TP)
(field (name Value) TEST))
(pins
(pin (num 1) (name ~) (type passive))))
(libpart (lib conn) (part USB_OTG)
(description "USB mini/micro connector")
(footprints
(fp USB*))
(fields
(field (name Reference) J)
(field (name Value) USB_OTG))
(pins
(pin (num 1) (name VBUS) (type power_in))
(pin (num 2) (name D-) (type passive))
(pin (num 3) (name D+) (type passive))
(pin (num 4) (name ID) (type passive))
(pin (num 5) (name GND) (type power_in))
(pin (num 6) (name Shield) (type passive))))
(libpart (lib tinyfpga) (part iCE40-LP8K-CM81)
(fields
(field (name Reference) U)
(field (name Value) iCE40-LP8K-CM81))
(pins
(pin (num A1) (name IOT_224) (type BiDi))
(pin (num A2) (name IOT_221) (type BiDi))
(pin (num A3) (name IOT_217) (type BiDi))
(pin (num A4) (name IOT_208) (type BiDi))
(pin (num A5) (name VCCIO_0) (type BiDi))
(pin (num A6) (name IOT_185) (type BiDi))
(pin (num A7) (name IOT_177) (type BiDi))
(pin (num A8) (name IOT_174) (type BiDi))
(pin (num A9) (name IOR_116) (type BiDi))
(pin (num B1) (name IOL_3A) (type BiDi))
(pin (num B2) (name IOL_2B) (type BiDi))
(pin (num B3) (name IOT_218) (type BiDi))
(pin (num B4) (name IOT_211) (type BiDi))
(pin (num B5) (name IOT_188) (type BiDi))
(pin (num B6) (name IOT_183) (type BiDi))
(pin (num B7) (name IOT_180) (type BiDi))
(pin (num B8) (name IOT_170) (type BiDi))
(pin (num B9) (name IOR_120) (type BiDi))
(pin (num C1) (name IOL_3B) (type BiDi))
(pin (num C2) (name IOL_2A) (type BiDi))
(pin (num C3) (name IOL_7B) (type BiDi))
(pin (num C4) (name IOT_198_GBIN0) (type BiDi))
(pin (num C5) (name IOT_197_GBIN1) (type BiDi))
(pin (num C6) (name VCCIO_1) (type BiDi))
(pin (num C7) (name VPP_FAST) (type BiDi))
(pin (num C8) (name VPP_2V5) (type BiDi))
(pin (num C9) (name IOR_148) (type BiDi))
(pin (num D1) (name IOL_10A) (type BiDi))
(pin (num D2) (name IOL_7A) (type BiDi))
(pin (num D3) (name IOL_13B_GBIN7) (type BiDi))
(pin (num D4) (name VCC) (type BiDi))
(pin (num D5) (name IOT_212) (type BiDi))
(pin (num D6) (name IOR_115) (type BiDi))
(pin (num D7) (name IOR_117) (type BiDi))
(pin (num D8) (name IOR_141_GBIN2) (type BiDi))
(pin (num D9) (name IOR_119) (type BiDi))
(pin (num E1) (name IOL_10B) (type BiDi))
(pin (num E2) (name IOL_13A) (type BiDi))
(pin (num E3) (name IOL_14A_GBIN6) (type BiDi))
(pin (num E4) (name IOL_14B) (type BiDi))
(pin (num E5) (name IOT_214) (type BiDi))
(pin (num E6) (name CDONE) (type BiDi))
(pin (num E7) (name IOR_118) (type BiDi))
(pin (num E8) (name IOR_140_GBIN3) (type BiDi))
(pin (num E9) (name VCC) (type BiDi))
(pin (num F1) (name IOL_22A) (type BiDi))
(pin (num F2) (name VCC) (type BiDi))
(pin (num F3) (name IOL_22B) (type BiDi))
(pin (num F4) (name GND) (type BiDi))
(pin (num F5) (name GND) (type BiDi))
(pin (num F6) (name GND) (type BiDi))
(pin (num F7) (name IOB_108_SS) (type BiDi))
(pin (num F8) (name IOR_113) (type BiDi))
(pin (num F9) (name GND) (type BiDi))
(pin (num G1) (name IOL_24B) (type BiDi))
(pin (num G2) (name IOL_26A) (type BiDi))
(pin (num G3) (name IOL_24A) (type BiDi))
(pin (num G4) (name IOB_81_GBIN5) (type BiDi))
(pin (num G5) (name IOB_103_CBSEL0) (type BiDi))
(pin (num G6) (name IOB_105_SDO) (type BiDi))
(pin (num G7) (name IOB_107_SCK) (type BiDi))
(pin (num G8) (name IOR_114) (type BiDi))
(pin (num G9) (name IOR_112) (type BiDi))
(pin (num H1) (name IOB_54) (type BiDi))
(pin (num H2) (name IOL_26B) (type BiDi))
(pin (num H3) (name VCCIO_3) (type BiDi))
(pin (num H4) (name IOB_82_GBIN4) (type BiDi))
(pin (num H5) (name IOB_104_CBSEL1) (type BiDi))
(pin (num H6) (name CRESET_B) (type BiDi))
(pin (num H7) (name IOB_106_SDI) (type BiDi))
(pin (num H8) (name VCC_SPI) (type BiDi))
(pin (num H9) (name IOR_111) (type BiDi))
(pin (num J1) (name IOB_55) (type BiDi))
(pin (num J2) (name IOB_56) (type BiDi))
(pin (num J3) (name IOB_57) (type BiDi))
(pin (num J4) (name IOB_70) (type BiDi))
(pin (num J5) (name VCCIO_2) (type BiDi))
(pin (num J6) (name GNDPLL0) (type BiDi))
(pin (num J7) (name VCCPLL0) (type BiDi))
(pin (num J8) (name IOR_109) (type BiDi))
(pin (num J9) (name IOR_110) (type BiDi)))))
(libraries
(library (logical switches)
(uri "C:\\Program Files\\KiCad\\share\\kicad\\library\\switches.lib"))
(library (logical tinyfpga)
(uri C:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-BX\board\tinyfpga.lib))
(library (logical device)
(uri "C:\\Program Files\\KiCad\\share\\kicad\\library\\device.lib"))
(library (logical conn)
(uri "C:\\Program Files\\KiCad\\share\\kicad\\library\\conn.lib")))
(nets
(net (code 1) (name 185)
(node (ref J2) (pin 4))
(node (ref U1) (pin A6)))
(net (code 2) (name +3V3)
(node (ref D1) (pin 2))
(node (ref J2) (pin 3))
(node (ref R10) (pin 1))
(node (ref C14) (pin 1))
(node (ref J4) (pin 3))
(node (ref C8) (pin 1))
(node (ref C2) (pin 1))
(node (ref U5) (pin 8))
(node (ref R5) (pin 1))
(node (ref C15) (pin 1))
(node (ref C16) (pin 1))
(node (ref U1) (pin A5))
(node (ref U1) (pin H3))
(node (ref U1) (pin B5))
(node (ref U1) (pin H8))
(node (ref U1) (pin C8))
(node (ref C5) (pin 1))
(node (ref C4) (pin 1))
(node (ref U1) (pin B9))
(node (ref U1) (pin C6))
(node (ref U1) (pin J5))
(node (ref U2) (pin 5))
(node (ref U3) (pin 4))
(node (ref U4) (pin 3))
(node (ref U4) (pin 1))
(node (ref U2) (pin 4))
(node (ref C10) (pin 1))
(node (ref R6) (pin 1))
(node (ref C9) (pin 1))
(node (ref U3) (pin 1))
(node (ref R7) (pin 1)))
(net (code 3) (name +5V)
(node (ref J2) (pin 1))
(node (ref U2) (pin 3))
(node (ref L1) (pin 1))
(node (ref C17) (pin 1))
(node (ref U2) (pin 1))
(node (ref C1) (pin 1)))
(net (code 4) (name 177)
(node (ref J2) (pin 6))
(node (ref U1) (pin A7)))
(net (code 5) (name 174)
(node (ref J2) (pin 8))
(node (ref U1) (pin A8)))
(net (code 6) (name 116)
(node (ref U1) (pin A9))
(node (ref J2) (pin 10)))
(net (code 7) (name 148)
(node (ref U1) (pin C9))
(node (ref J2) (pin 11)))
(net (code 8) (name 119)
(node (ref J2) (pin 13))
(node (ref U1) (pin D9)))
(net (code 9) (name GND)
(node (ref C4) (pin 2))
(node (ref C1) (pin 2))
(node (ref C3) (pin 2))
(node (ref C8) (pin 2))
(node (ref C17) (pin 2))
(node (ref C5) (pin 2))
(node (ref J4) (pin 15))
(node (ref J4) (pin 16))
(node (ref C10) (pin 2))
(node (ref U5) (pin 4))
(node (ref C12) (pin 2))
(node (ref C11) (pin 2))
(node (ref C14) (pin 2))
(node (ref C2) (pin 2))
(node (ref U1) (pin F5))
(node (ref C15) (pin 2))
(node (ref C9) (pin 2))
(node (ref C13) (pin 2))
(node (ref U1) (pin E4))
(node (ref U2) (pin 2))
(node (ref U3) (pin 2))
(node (ref U1) (pin F6))
(node (ref J3) (pin 5))
(node (ref R8) (pin 2))
(node (ref R9) (pin 2))
(node (ref J1) (pin 1))
(node (ref J3) (pin 6))
(node (ref J4) (pin 4))
(node (ref U4) (pin 2))
(node (ref J2) (pin 2))
(node (ref SW1) (pin 1))
(node (ref C16) (pin 2))
(node (ref U1) (pin F9))
(node (ref U1) (pin E5))
(node (ref U1) (pin F4)))
(net (code 10) (name 111)
(node (ref U1) (pin H9))
(node (ref J2) (pin 14)))
(net (code 11) (name +1V2)
(node (ref U1) (pin E9))
(node (ref U1) (pin D4))
(node (ref U1) (pin F2))
(node (ref U1) (pin E3))
(node (ref U1) (pin F1))
(node (ref C11) (pin 1))
(node (ref C13) (pin 1))
(node (ref C12) (pin 1))
(node (ref TP3) (pin 1))
(node (ref R4) (pin 2))
(node (ref C3) (pin 1))
(node (ref U4) (pin 5)))
(net (code 12) (name 54)
(node (ref U1) (pin H1))
(node (ref J1) (pin 12)))
(net (code 13) (name 221)
(node (ref U1) (pin A2))
(node (ref J1) (pin 2)))
(net (code 14) (name 224)
(node (ref J1) (pin 3))
(node (ref U1) (pin A1)))
(net (code 15) (name 3A)
(node (ref U1) (pin B1))
(node (ref J1) (pin 4)))
(net (code 16) (name 3B)
(node (ref J1) (pin 6))
(node (ref U1) (pin C1)))
(net (code 17) (name 10A)
(node (ref U1) (pin D1))
(node (ref J1) (pin 8)))
(net (code 18) (name 13A)
(node (ref U1) (pin E2))
(node (ref J1) (pin 9)))
(net (code 19) (name 10B)
(node (ref U1) (pin E1))
(node (ref J1) (pin 10)))
(net (code 20) (name 26A)
(node (ref J1) (pin 11))
(node (ref U1) (pin G2)))
(net (code 21) (name 55)
(node (ref J1) (pin 13))
(node (ref U1) (pin J1)))
(net (code 22) (name CRESET_B)
(node (ref SW1) (pin 2))
(node (ref U1) (pin H6))
(node (ref TP2) (pin 1))
(node (ref R6) (pin 2)))
(net (code 23) (name "Net-(C6-Pad1)")
(node (ref C7) (pin 1))
(node (ref C6) (pin 1))
(node (ref U1) (pin J6)))
(net (code 24) (name "Net-(C6-Pad2)")
(node (ref R4) (pin 1))
(node (ref C6) (pin 2))
(node (ref U1) (pin J7))
(node (ref C7) (pin 2)))
(net (code 25) (name LED)
(node (ref U1) (pin B3))
(node (ref J5) (pin 3))
(node (ref D2) (pin 2)))
(net (code 26) (name SDO)
(node (ref U1) (pin H5))
(node (ref J4) (pin 13))
(node (ref U5) (pin 5))
(node (ref U1) (pin G6)))
(net (code 27) (name CLK)
(node (ref U1) (pin B2))
(node (ref J5) (pin 1))
(node (ref U3) (pin 3)))
(net (code 28) (name USB_P)
(node (ref R2) (pin 1))
(node (ref U1) (pin B4))
(node (ref J5) (pin 5)))
(net (code 29) (name USB_N)
(node (ref R3) (pin 1))
(node (ref J5) (pin 6))
(node (ref U1) (pin A4)))
(net (code 30) (name "Net-(D1-Pad1)")
(node (ref D1) (pin 1))
(node (ref R8) (pin 1)))
(net (code 31) (name "Net-(D2-Pad1)")
(node (ref R9) (pin 1))
(node (ref D2) (pin 1)))
(net (code 32) (name 109)
(node (ref J4) (pin 9))
(node (ref U5) (pin 7))
(node (ref R10) (pin 2))
(node (ref U1) (pin J8)))
(net (code 33) (name 56)
(node (ref J5) (pin 2))
(node (ref U1) (pin J2)))
(net (code 34) (name 140)
(node (ref J4) (pin 1))
(node (ref U1) (pin E8)))
(net (code 35) (name 24B)
(node (ref U1) (pin G1))
(node (ref J4) (pin 2)))
(net (code 36) (name 82)
(node (ref TP1) (pin 1))
(node (ref J4) (pin 10))
(node (ref R7) (pin 2))
(node (ref U5) (pin 3))
(node (ref U1) (pin H4)))
(net (code 37) (name SCK)
(node (ref J4) (pin 11))
(node (ref U1) (pin G7))
(node (ref U5) (pin 6))
(node (ref U1) (pin G8)))
(net (code 38) (name SDI)
(node (ref U1) (pin H7))
(node (ref J4) (pin 12))
(node (ref U5) (pin 2)))
(net (code 39) (name SS)
(node (ref U1) (pin F7))
(node (ref U1) (pin F8))
(node (ref R5) (pin 2))
(node (ref U5) (pin 1))
(node (ref J4) (pin 14)))
(net (code 40) (name 26B)
(node (ref J1) (pin 14))
(node (ref U1) (pin H2)))
(net (code 41) (name 183)
(node (ref J2) (pin 5))
(node (ref U1) (pin B6)))
(net (code 42) (name 7A)
(node (ref J1) (pin 7))
(node (ref U1) (pin D2)))
(net (code 43) (name 180)
(node (ref J2) (pin 7))
(node (ref U1) (pin B7)))
(net (code 44) (name 170)
(node (ref U1) (pin B8))
(node (ref J2) (pin 9)))
(net (code 45) (name USB_PU)
(node (ref J5) (pin 4))
(node (ref R1) (pin 2))
(node (ref U1) (pin A3)))
(net (code 46) (name 2A)
(node (ref J1) (pin 5))
(node (ref U1) (pin C2)))
(net (code 47) (name 70)
(node (ref U1) (pin J4))
(node (ref J4) (pin 8)))
(net (code 48) (name 110)
(node (ref U1) (pin J9))
(node (ref J4) (pin 5)))
(net (code 49) (name 112)
(node (ref U1) (pin G9))
(node (ref J4) (pin 7)))
(net (code 50) (name 57)
(node (ref U1) (pin J3))
(node (ref J4) (pin 6)))
(net (code 51) (name 141)
(node (ref U1) (pin D8))
(node (ref J2) (pin 12)))
(net (code 52) (name VPP_FAST)
(node (ref U1) (pin C7)))
(net (code 53) (name CDONE)
(node (ref U1) (pin E6)))
(net (code 54) (name 115)
(node (ref U1) (pin D6)))
(net (code 55) (name 212)
(node (ref U1) (pin D5)))
(net (code 56) (name 81_GBIN5)
(node (ref U1) (pin G4)))
(net (code 57) (name "Net-(U1-PadC3)")
(node (ref U1) (pin C3)))
(net (code 58) (name "Net-(U1-PadD3)")
(node (ref U1) (pin D3)))
(net (code 59) (name "Net-(U1-PadF3)")
(node (ref U1) (pin F3)))
(net (code 60) (name 24A)
(node (ref U1) (pin G3)))
(net (code 61) (name "Net-(U1-PadD7)")
(node (ref U1) (pin D7)))
(net (code 62) (name "Net-(U1-PadE7)")
(node (ref U1) (pin E7)))
(net (code 63) (name "Net-(U1-PadC5)")
(node (ref U1) (pin C5)))
(net (code 64) (name "Net-(U1-PadC4)")
(node (ref U1) (pin C4)))
(net (code 65) (name "Net-(J3-Pad1)")
(node (ref L1) (pin 2))
(node (ref J3) (pin 1)))
(net (code 66) (name "Net-(J3-Pad2)")
(node (ref J3) (pin 2))
(node (ref R3) (pin 2)))
(net (code 67) (name "Net-(J3-Pad3)")
(node (ref R1) (pin 1))
(node (ref R2) (pin 2))
(node (ref J3) (pin 3)))
(net (code 68) (name "Net-(J3-Pad4)")
(node (ref J3) (pin 4)))
(net (code 69) (name "Net-(U4-Pad4)")
(node (ref U4) (pin 4)))
(net (code 70) (name "Net-(U1-PadG5)")
(node (ref U1) (pin G5)))))

75
board/TinyFPGA-BX.pro Normal file
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@@ -0,0 +1,75 @@
update=3/30/2018 3:46:56 PM
version=1
last_client=kicad
[general]
version=1
RootSch=
BoardNm=
[cvpcb]
version=1
NetIExt=net
[eeschema]
version=1
LibDir=
[eeschema/libraries]
LibName1=power
LibName2=device
LibName3=switches
LibName4=relays
LibName5=motors
LibName6=transistors
LibName7=conn
LibName8=linear
LibName9=regul
LibName10=74xx
LibName11=cmos4000
LibName12=adc-dac
LibName13=memory
LibName14=xilinx
LibName15=microcontrollers
LibName16=dsp
LibName17=microchip
LibName18=analog_switches
LibName19=motorola
LibName20=texas
LibName21=intel
LibName22=audio
LibName23=interface
LibName24=digital-audio
LibName25=philips
LibName26=display
LibName27=cypress
LibName28=siliconi
LibName29=opto
LibName30=atmel
LibName31=contrib
LibName32=valves
[pcbnew]
version=1
PageLayoutDescrFile=
LastNetListRead=TinyFPGA-BX.net
PadDrill=0
PadDrillOvalY=0
PadSizeH=0.09999999999999999
PadSizeV=0.09999999999999999
PcbTextSizeV=1.5
PcbTextSizeH=1.5
PcbTextThickness=0.3
ModuleTextSizeV=1
ModuleTextSizeH=1
ModuleTextSizeThickness=0.15
SolderMaskClearance=0.075
SolderMaskMinWidth=0
DrawSegmentWidth=0.2
BoardOutlineThickness=0.15
ModuleOutlineThickness=0.15
[schematic_editor]
version=1
PageLayoutDescrFile=
PlotDirectoryName=
SubpartIdSeparator=0
SubpartFirstId=65
NetFmtName=
SpiceForceRefPrefix=0
SpiceUseNetNumbers=0
LabSize=60

1683
board/TinyFPGA-BX.sch Normal file
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File diff suppressed because it is too large Load Diff

850
board/TinyFPGA-BX.xml Normal file
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@@ -0,0 +1,850 @@
<?xml version="1.0" encoding="UTF-8"?>
<export version="D">
<design>
<source>C:/Users/lvale/Documents/TinyFPGA/TinyFPGA-ICE/TinyFPGA-ICE.sch</source>
<date>5/24/2017 7:27:29 AM</date>
<tool>Eeschema 4.0.6</tool>
<sheet number="1" name="/" tstamps="/">
<title_block>
<title/>
<company/>
<rev/>
<date/>
<source>TinyFPGA-ICE.sch</source>
<comment number="1" value=""/>
<comment number="2" value=""/>
<comment number="3" value=""/>
<comment number="4" value=""/>
</title_block>
</sheet>
</design>
<components>
<comp ref="U1">
<value>iCE40-LP8K-CM81</value>
<footprint>tinyfpga:CM81</footprint>
<libsource lib="tinyfpga" part="iCE40-LP8K-CM81"/>
<sheetpath names="/" tstamps="/"/>
<tstamp>591007FD</tstamp>
</comp>
<comp ref="J1">
<value>CONN_01X14</value>
<footprint>Pin_Headers:Pin_Header_Straight_1x14_Pitch2.54mm</footprint>
<libsource lib="conn" part="CONN_01X14"/>
<sheetpath names="/" tstamps="/"/>
<tstamp>591076F8</tstamp>
</comp>
<comp ref="J2">
<value>CONN_01X14</value>
<footprint>Pin_Headers:Pin_Header_Straight_1x14_Pitch2.54mm</footprint>
<libsource lib="conn" part="CONN_01X14"/>
<sheetpath names="/" tstamps="/"/>
<tstamp>5910778F</tstamp>
</comp>
<comp ref="J3">
<value>USB_OTG</value>
<footprint>Connectors:USB_Micro-B</footprint>
<libsource lib="conn" part="USB_OTG"/>
<sheetpath names="/" tstamps="/"/>
<tstamp>5918C75D</tstamp>
</comp>
<comp ref="SW1">
<value>SW_Push</value>
<footprint>tinyfpga:PTS_810_SMT_Switch</footprint>
<libsource lib="switches" part="SW_Push"/>
<sheetpath names="/" tstamps="/"/>
<tstamp>5918CB81</tstamp>
</comp>
<comp ref="U4">
<value>MIC5365-1.2YC5-TR</value>
<footprint>tinyfpga:SC-70-C5</footprint>
<libsource lib="tinyfpga" part="MIC5365-1.2YC5-TR"/>
<sheetpath names="/" tstamps="/"/>
<tstamp>591A9EDF</tstamp>
</comp>
<comp ref="U2">
<value>MIC5504-3.3YM5-TR</value>
<footprint>tinyfpga:SC-70-C5</footprint>
<libsource lib="tinyfpga" part="MIC5504-3.3YM5-TR"/>
<sheetpath names="/" tstamps="/"/>
<tstamp>591A9F5A</tstamp>
</comp>
<comp ref="U3">
<value>DSC6001CI2A-016.0000T</value>
<footprint>tinyfpga:CDFN3225-4LD-PL-1</footprint>
<libsource lib="tinyfpga" part="DSC6001CI2A-016.0000T"/>
<sheetpath names="/" tstamps="/"/>
<tstamp>591A9FD7</tstamp>
</comp>
<comp ref="U5">
<value>AT25SF041-SSHD-B</value>
<footprint>Housings_SOIC:SOIC-8-1EP_3.9x4.9mm_Pitch1.27mm</footprint>
<libsource lib="tinyfpga" part="AT25SF041-SSHD-B"/>
<sheetpath names="/" tstamps="/"/>
<tstamp>591BDF5F</tstamp>
</comp>
<comp ref="C2">
<value>1uF</value>
<footprint>Capacitors_SMD:C_0402_NoSilk</footprint>
<libsource lib="device" part="C"/>
<sheetpath names="/" tstamps="/"/>
<tstamp>591BF1F2</tstamp>
</comp>
<comp ref="C3">
<value>1uF</value>
<footprint>Capacitors_SMD:C_0402_NoSilk</footprint>
<libsource lib="device" part="C"/>
<sheetpath names="/" tstamps="/"/>
<tstamp>591BF26D</tstamp>
</comp>
<comp ref="C1">
<value>1uF</value>
<footprint>Capacitors_SMD:C_0402_NoSilk</footprint>
<libsource lib="device" part="C"/>
<sheetpath names="/" tstamps="/"/>
<tstamp>591C09B3</tstamp>
</comp>
<comp ref="C4">
<value>1uF</value>
<footprint>Capacitors_SMD:C_0402_NoSilk</footprint>
<libsource lib="device" part="C"/>
<sheetpath names="/" tstamps="/"/>
<tstamp>591C0A32</tstamp>
</comp>
<comp ref="L1">
<value>Bead</value>
<footprint>Inductors_SMD:L_0603</footprint>
<libsource lib="device" part="Ferrite_Bead_Small"/>
<sheetpath names="/" tstamps="/"/>
<tstamp>591C2A75</tstamp>
</comp>
<comp ref="R2">
<value>68</value>
<footprint>Resistors_SMD:R_0402_NoSilk</footprint>
<libsource lib="device" part="R"/>
<sheetpath names="/" tstamps="/"/>
<tstamp>591D2293</tstamp>
</comp>
<comp ref="R3">
<value>68</value>
<footprint>Resistors_SMD:R_0402_NoSilk</footprint>
<libsource lib="device" part="R"/>
<sheetpath names="/" tstamps="/"/>
<tstamp>591D2392</tstamp>
</comp>
<comp ref="R1">
<value>1.5k</value>
<footprint>Resistors_SMD:R_0402_NoSilk</footprint>
<libsource lib="device" part="R"/>
<sheetpath names="/" tstamps="/"/>
<tstamp>591D2427</tstamp>
</comp>
<comp ref="C5">
<value>100nF</value>
<footprint>Capacitors_SMD:C_0402_NoSilk</footprint>
<libsource lib="device" part="C"/>
<sheetpath names="/" tstamps="/"/>
<tstamp>591E10BF</tstamp>
</comp>
<comp ref="C8">
<value>100nF</value>
<footprint>Capacitors_SMD:C_0402_NoSilk</footprint>
<libsource lib="device" part="C"/>
<sheetpath names="/" tstamps="/"/>
<tstamp>591E1ADB</tstamp>
</comp>
<comp ref="C7">
<value>100nF</value>
<footprint>Capacitors_SMD:C_0402_NoSilk</footprint>
<libsource lib="device" part="C"/>
<sheetpath names="/" tstamps="/"/>
<tstamp>591E2ADF</tstamp>
</comp>
<comp ref="C6">
<value>10uF</value>
<footprint>Capacitors_SMD:C_0603</footprint>
<libsource lib="device" part="C"/>
<sheetpath names="/" tstamps="/"/>
<tstamp>591E2B9D</tstamp>
</comp>
<comp ref="R4">
<value>100</value>
<footprint>Resistors_SMD:R_0402_NoSilk</footprint>
<libsource lib="device" part="R"/>
<sheetpath names="/" tstamps="/"/>
<tstamp>591E2BF1</tstamp>
</comp>
<comp ref="C9">
<value>100nF</value>
<footprint>Capacitors_SMD:C_0402_NoSilk</footprint>
<libsource lib="device" part="C_Small"/>
<sheetpath names="/" tstamps="/"/>
<tstamp>591E9D9B</tstamp>
</comp>
<comp ref="C10">
<value>100nF</value>
<footprint>Capacitors_SMD:C_0402_NoSilk</footprint>
<libsource lib="device" part="C_Small"/>
<sheetpath names="/" tstamps="/"/>
<tstamp>591E9E78</tstamp>
</comp>
<comp ref="C11">
<value>100nF</value>
<footprint>Capacitors_SMD:C_0402_NoSilk</footprint>
<libsource lib="device" part="C_Small"/>
<sheetpath names="/" tstamps="/"/>
<tstamp>591E9EF1</tstamp>
</comp>
<comp ref="C12">
<value>10nF</value>
<footprint>Capacitors_SMD:C_0402_NoSilk</footprint>
<libsource lib="device" part="C_Small"/>
<sheetpath names="/" tstamps="/"/>
<tstamp>591E9FF1</tstamp>
</comp>
<comp ref="C13">
<value>10nF</value>
<footprint>Capacitors_SMD:C_0402_NoSilk</footprint>
<libsource lib="device" part="C_Small"/>
<sheetpath names="/" tstamps="/"/>
<tstamp>591EA15E</tstamp>
</comp>
<comp ref="C14">
<value>10nF</value>
<footprint>Capacitors_SMD:C_0402_NoSilk</footprint>
<libsource lib="device" part="C_Small"/>
<sheetpath names="/" tstamps="/"/>
<tstamp>591EA1D8</tstamp>
</comp>
<comp ref="C15">
<value>10nF</value>
<footprint>Capacitors_SMD:C_0402_NoSilk</footprint>
<libsource lib="device" part="C_Small"/>
<sheetpath names="/" tstamps="/"/>
<tstamp>591EA257</tstamp>
</comp>
<comp ref="R5">
<value>10k</value>
<footprint>Resistors_SMD:R_0402_NoSilk</footprint>
<libsource lib="device" part="R"/>
<sheetpath names="/" tstamps="/"/>
<tstamp>591EBB96</tstamp>
</comp>
<comp ref="C16">
<value>100nF</value>
<footprint>Capacitors_SMD:C_0402_NoSilk</footprint>
<libsource lib="device" part="C_Small"/>
<sheetpath names="/" tstamps="/"/>
<tstamp>591EA04F</tstamp>
</comp>
<comp ref="R6">
<value>R</value>
<footprint>Resistors_SMD:R_0402</footprint>
<libsource lib="device" part="R"/>
<sheetpath names="/" tstamps="/"/>
<tstamp>592015DC</tstamp>
</comp>
<comp ref="C17">
<value>10uF</value>
<footprint>Capacitors_SMD:C_0603</footprint>
<libsource lib="device" part="C"/>
<sheetpath names="/" tstamps="/"/>
<tstamp>592061E2</tstamp>
</comp>
<comp ref="R7">
<value>10k</value>
<footprint>Resistors_SMD:R_0402_NoSilk</footprint>
<libsource lib="device" part="R"/>
<sheetpath names="/" tstamps="/"/>
<tstamp>5922D14B</tstamp>
</comp>
<comp ref="TP1">
<value>TEST</value>
<footprint>Measurement_Points:Measurement_Point_Round-SMD-Pad_Small</footprint>
<libsource lib="device" part="TEST"/>
<sheetpath names="/" tstamps="/"/>
<tstamp>5922E3E0</tstamp>
</comp>
<comp ref="TP2">
<value>TEST</value>
<footprint>Measurement_Points:Measurement_Point_Round-SMD-Pad_Small</footprint>
<libsource lib="device" part="TEST"/>
<sheetpath names="/" tstamps="/"/>
<tstamp>5923D3AB</tstamp>
</comp>
</components>
<libparts>
<libpart lib="tinyfpga" part="AT25SF041-SSHD-B">
<fields>
<field name="Reference">U</field>
<field name="Value">AT25SF041-SSHD-B</field>
</fields>
<pins>
<pin num="1" name="!CS" type="BiDi"/>
<pin num="2" name="SO" type="BiDi"/>
<pin num="3" name="!WP" type="BiDi"/>
<pin num="4" name="GND" type="BiDi"/>
<pin num="5" name="SI" type="BiDi"/>
<pin num="6" name="SCK" type="BiDi"/>
<pin num="7" name="!HOLD" type="BiDi"/>
<pin num="8" name="VCC" type="BiDi"/>
</pins>
</libpart>
<libpart lib="device" part="C">
<description>Unpolarized capacitor</description>
<footprints>
<fp>C_*</fp>
</footprints>
<fields>
<field name="Reference">C</field>
<field name="Value">C</field>
</fields>
<pins>
<pin num="1" name="~" type="passive"/>
<pin num="2" name="~" type="passive"/>
</pins>
</libpart>
<libpart lib="conn" part="CONN_01X14">
<description>Connector, single row, 01x14, pin header</description>
<footprints>
<fp>Pin_Header_Straight_1X*</fp>
<fp>Pin_Header_Angled_1X*</fp>
<fp>Socket_Strip_Straight_1X*</fp>
<fp>Socket_Strip_Angled_1X*</fp>
</footprints>
<fields>
<field name="Reference">J</field>
<field name="Value">CONN_01X14</field>
</fields>
<pins>
<pin num="1" name="P1" type="passive"/>
<pin num="2" name="P2" type="passive"/>
<pin num="3" name="P3" type="passive"/>
<pin num="4" name="P4" type="passive"/>
<pin num="5" name="P5" type="passive"/>
<pin num="6" name="P6" type="passive"/>
<pin num="7" name="P7" type="passive"/>
<pin num="8" name="P8" type="passive"/>
<pin num="9" name="P9" type="passive"/>
<pin num="10" name="P10" type="passive"/>
<pin num="11" name="P11" type="passive"/>
<pin num="12" name="P12" type="passive"/>
<pin num="13" name="P13" type="passive"/>
<pin num="14" name="P14" type="passive"/>
</pins>
</libpart>
<libpart lib="device" part="C_Small">
<description>Unpolarized capacitor</description>
<footprints>
<fp>C_*</fp>
</footprints>
<fields>
<field name="Reference">C</field>
<field name="Value">C_Small</field>
</fields>
<pins>
<pin num="1" name="~" type="passive"/>
<pin num="2" name="~" type="passive"/>
</pins>
</libpart>
<libpart lib="tinyfpga" part="DSC6001CI2A-016.0000T">
<fields>
<field name="Reference">U</field>
<field name="Value">DSC6001CI2A-016.0000T</field>
</fields>
<pins>
<pin num="1" name="OE" type="BiDi"/>
<pin num="2" name="GND" type="BiDi"/>
<pin num="3" name="OUT" type="BiDi"/>
<pin num="4" name="VDD" type="BiDi"/>
</pins>
</libpart>
<libpart lib="device" part="Ferrite_Bead_Small">
<description>Ferrite bead, small symbol</description>
<footprints>
<fp>Inductor_*</fp>
<fp>L_*</fp>
<fp>*Ferrite*</fp>
</footprints>
<fields>
<field name="Reference">L</field>
<field name="Value">Ferrite_Bead_Small</field>
</fields>
<pins>
<pin num="1" name="~" type="passive"/>
<pin num="2" name="~" type="passive"/>
</pins>
</libpart>
<libpart lib="tinyfpga" part="MIC5365-1.2YC5-TR">
<fields>
<field name="Reference">U</field>
<field name="Value">MIC5365-1.2YC5-TR</field>
</fields>
<pins>
<pin num="1" name="VIN" type="BiDi"/>
<pin num="2" name="GND" type="BiDi"/>
<pin num="3" name="EN" type="BiDi"/>
<pin num="4" name="NC" type="BiDi"/>
<pin num="5" name="VOUT" type="BiDi"/>
</pins>
</libpart>
<libpart lib="tinyfpga" part="MIC5504-3.3YM5-TR">
<fields>
<field name="Reference">U</field>
<field name="Value">MIC5504-3.3YM5-TR</field>
</fields>
<pins>
<pin num="1" name="VIN" type="BiDi"/>
<pin num="2" name="GND" type="BiDi"/>
<pin num="3" name="EN" type="BiDi"/>
<pin num="4" name="NC" type="BiDi"/>
<pin num="5" name="VOUT" type="BiDi"/>
</pins>
</libpart>
<libpart lib="device" part="R">
<description>Resistor</description>
<footprints>
<fp>R_*</fp>
<fp>R_*</fp>
</footprints>
<fields>
<field name="Reference">R</field>
<field name="Value">R</field>
</fields>
<pins>
<pin num="1" name="~" type="passive"/>
<pin num="2" name="~" type="passive"/>
</pins>
</libpart>
<libpart lib="switches" part="SW_Push">
<description>Push button switch, generic, two pins</description>
<fields>
<field name="Reference">SW</field>
<field name="Value">SW_Push</field>
</fields>
<pins>
<pin num="1" name="1" type="passive"/>
<pin num="2" name="2" type="passive"/>
</pins>
</libpart>
<libpart lib="device" part="TEST">
<description>Testpoint, connection for test equipment</description>
<fields>
<field name="Reference">TP</field>
<field name="Value">TEST</field>
</fields>
<pins>
<pin num="1" name="~" type="passive"/>
</pins>
</libpart>
<libpart lib="conn" part="USB_OTG">
<description>USB mini/micro connector</description>
<footprints>
<fp>USB*</fp>
</footprints>
<fields>
<field name="Reference">J</field>
<field name="Value">USB_OTG</field>
</fields>
<pins>
<pin num="1" name="VBUS" type="power_in"/>
<pin num="2" name="D-" type="passive"/>
<pin num="3" name="D+" type="passive"/>
<pin num="4" name="ID" type="passive"/>
<pin num="5" name="GND" type="power_in"/>
<pin num="6" name="Shield" type="passive"/>
</pins>
</libpart>
<libpart lib="tinyfpga" part="iCE40-LP8K-CM81">
<fields>
<field name="Reference">U</field>
<field name="Value">iCE40-LP8K-CM81</field>
</fields>
<pins>
<pin num="A1" name="IOT_224" type="BiDi"/>
<pin num="A2" name="IOT_221" type="BiDi"/>
<pin num="A3" name="IOT_217" type="BiDi"/>
<pin num="A4" name="IOT_208" type="BiDi"/>
<pin num="A5" name="VCCIO_0" type="BiDi"/>
<pin num="A6" name="IOT_185" type="BiDi"/>
<pin num="A7" name="IOT_177" type="BiDi"/>
<pin num="A8" name="IOT_174" type="BiDi"/>
<pin num="A9" name="IOR_116" type="BiDi"/>
<pin num="B1" name="IOL_3A" type="BiDi"/>
<pin num="B2" name="IOL_2B" type="BiDi"/>
<pin num="B3" name="IOT_218" type="BiDi"/>
<pin num="B4" name="IOT_211" type="BiDi"/>
<pin num="B5" name="IOT_188" type="BiDi"/>
<pin num="B6" name="IOT_183" type="BiDi"/>
<pin num="B7" name="IOT_180" type="BiDi"/>
<pin num="B8" name="IOT_170" type="BiDi"/>
<pin num="B9" name="IOR_120" type="BiDi"/>
<pin num="C1" name="IOL_3B" type="BiDi"/>
<pin num="C2" name="IOL_2A" type="BiDi"/>
<pin num="C3" name="IOL_7B" type="BiDi"/>
<pin num="C4" name="IOT_198_GBIN0" type="BiDi"/>
<pin num="C5" name="IOT_197_GBIN1" type="BiDi"/>
<pin num="C6" name="VCCIO_1" type="BiDi"/>
<pin num="C7" name="VPP_FAST" type="BiDi"/>
<pin num="C8" name="VPP_2V5" type="BiDi"/>
<pin num="C9" name="IOR_148" type="BiDi"/>
<pin num="D1" name="IOL_10A" type="BiDi"/>
<pin num="D2" name="IOL_7A" type="BiDi"/>
<pin num="D3" name="IOL_13B_GBIN7" type="BiDi"/>
<pin num="D4" name="VCC" type="BiDi"/>
<pin num="D5" name="IOT_212" type="BiDi"/>
<pin num="D6" name="IOR_115" type="BiDi"/>
<pin num="D7" name="IOR_117" type="BiDi"/>
<pin num="D8" name="IOR_141_GBIN2" type="BiDi"/>
<pin num="D9" name="IOR_119" type="BiDi"/>
<pin num="E1" name="IOL_10B" type="BiDi"/>
<pin num="E2" name="IOL_13A" type="BiDi"/>
<pin num="E3" name="IOL_14A_GBIN6" type="BiDi"/>
<pin num="E4" name="IOL_14B" type="BiDi"/>
<pin num="E5" name="IOT_214" type="BiDi"/>
<pin num="E6" name="CDONE" type="BiDi"/>
<pin num="E7" name="IOR_118" type="BiDi"/>
<pin num="E8" name="IOR_140_GBIN3" type="BiDi"/>
<pin num="E9" name="VCC" type="BiDi"/>
<pin num="F1" name="IOL_22A" type="BiDi"/>
<pin num="F2" name="VCC" type="BiDi"/>
<pin num="F3" name="IOL_22B" type="BiDi"/>
<pin num="F4" name="GND" type="BiDi"/>
<pin num="F5" name="GND" type="BiDi"/>
<pin num="F6" name="GND" type="BiDi"/>
<pin num="F7" name="IOB_108_SS" type="BiDi"/>
<pin num="F8" name="IOR_113" type="BiDi"/>
<pin num="F9" name="GND" type="BiDi"/>
<pin num="G1" name="IOL_24B" type="BiDi"/>
<pin num="G2" name="IOL_26A" type="BiDi"/>
<pin num="G3" name="IOL_24A" type="BiDi"/>
<pin num="G4" name="IOB_81_GBIN5" type="BiDi"/>
<pin num="G5" name="IOB_103_CBSEL0" type="BiDi"/>
<pin num="G6" name="IOB_105_SDO" type="BiDi"/>
<pin num="G7" name="IOB_107_SCK" type="BiDi"/>
<pin num="G8" name="IOR_114" type="BiDi"/>
<pin num="G9" name="IOR_112" type="BiDi"/>
<pin num="H1" name="IOB_54" type="BiDi"/>
<pin num="H2" name="IOL_26B" type="BiDi"/>
<pin num="H3" name="VCCIO_3" type="BiDi"/>
<pin num="H4" name="IOB_82_GBIN4" type="BiDi"/>
<pin num="H5" name="IOB_104_CBSEL1" type="BiDi"/>
<pin num="H6" name="CRESET_B" type="BiDi"/>
<pin num="H7" name="IOB_106_SDI" type="BiDi"/>
<pin num="H8" name="VCC_SPI" type="BiDi"/>
<pin num="H9" name="IOR_111" type="BiDi"/>
<pin num="J1" name="IOB_55" type="BiDi"/>
<pin num="J2" name="IOB_56" type="BiDi"/>
<pin num="J3" name="IOB_57" type="BiDi"/>
<pin num="J4" name="IOB_70" type="BiDi"/>
<pin num="J5" name="VCCIO_2" type="BiDi"/>
<pin num="J6" name="GNDPLL0" type="BiDi"/>
<pin num="J7" name="VCCPLL0" type="BiDi"/>
<pin num="J8" name="IOR_109" type="BiDi"/>
<pin num="J9" name="IOR_110" type="BiDi"/>
</pins>
</libpart>
</libparts>
<libraries>
<library logical="conn">
<uri>C:\Program Files\KiCad\share\kicad\library\conn.lib</uri>
</library>
<library logical="device">
<uri>C:\Program Files\KiCad\share\kicad\library\device.lib</uri>
</library>
<library logical="switches">
<uri>C:\Program Files\KiCad\share\kicad\library\switches.lib</uri>
</library>
<library logical="tinyfpga">
<uri>C:\Users\lvale\Documents\TinyFPGA\tinyfpga.lib</uri>
</library>
</libraries>
<nets>
<net code="1" name="SDI">
<node ref="J2" pin="13"/>
<node ref="U1" pin="H7"/>
<node ref="U5" pin="5"/>
<node ref="U1" pin="J8"/>
</net>
<net code="2" name="SS">
<node ref="U1" pin="G9"/>
<node ref="U1" pin="F7"/>
<node ref="J2" pin="11"/>
<node ref="U5" pin="1"/>
<node ref="U1" pin="F8"/>
<node ref="R5" pin="2"/>
</net>
<net code="3" name="SDO">
<node ref="U1" pin="H4"/>
<node ref="U1" pin="G6"/>
<node ref="J2" pin="14"/>
<node ref="U1" pin="G5"/>
<node ref="U1" pin="J3"/>
<node ref="U5" pin="2"/>
</net>
<net code="4" name="SCK">
<node ref="U1" pin="G8"/>
<node ref="U5" pin="6"/>
<node ref="U1" pin="G7"/>
<node ref="U1" pin="H9"/>
<node ref="J2" pin="12"/>
</net>
<net code="5" name="+3V3">
<node ref="C15" pin="1"/>
<node ref="C14" pin="1"/>
<node ref="U1" pin="B7"/>
<node ref="U1" pin="B6"/>
<node ref="U1" pin="B8"/>
<node ref="C16" pin="1"/>
<node ref="U1" pin="J2"/>
<node ref="U1" pin="B9"/>
<node ref="R5" pin="1"/>
<node ref="R6" pin="1"/>
<node ref="U1" pin="C6"/>
<node ref="U1" pin="J5"/>
<node ref="U1" pin="A5"/>
<node ref="U1" pin="H3"/>
<node ref="U1" pin="H8"/>
<node ref="U1" pin="C8"/>
<node ref="C2" pin="1"/>
<node ref="C8" pin="1"/>
<node ref="C4" pin="1"/>
<node ref="U4" pin="3"/>
<node ref="J2" pin="2"/>
<node ref="C5" pin="1"/>
<node ref="U1" pin="J9"/>
<node ref="C9" pin="1"/>
<node ref="C10" pin="1"/>
<node ref="R1" pin="2"/>
<node ref="U3" pin="4"/>
<node ref="U3" pin="1"/>
<node ref="U5" pin="8"/>
<node ref="U2" pin="5"/>
<node ref="U2" pin="4"/>
<node ref="U4" pin="1"/>
</net>
<net code="6" name="+1V2">
<node ref="C11" pin="1"/>
<node ref="U1" pin="D4"/>
<node ref="U4" pin="5"/>
<node ref="C12" pin="1"/>
<node ref="J2" pin="3"/>
<node ref="C13" pin="1"/>
<node ref="R4" pin="2"/>
<node ref="U1" pin="F1"/>
<node ref="U1" pin="F2"/>
<node ref="U1" pin="D2"/>
<node ref="U1" pin="E2"/>
<node ref="U1" pin="D3"/>
<node ref="C3" pin="1"/>
<node ref="U1" pin="E9"/>
</net>
<net code="7" name="Net-(C6-Pad1)">
<node ref="C7" pin="1"/>
<node ref="U1" pin="J6"/>
<node ref="C6" pin="1"/>
</net>
<net code="8" name="Net-(C6-Pad2)">
<node ref="U1" pin="J7"/>
<node ref="R4" pin="1"/>
<node ref="C6" pin="2"/>
<node ref="C7" pin="2"/>
</net>
<net code="9" name="Net-(J3-Pad1)">
<node ref="L1" pin="2"/>
<node ref="J3" pin="1"/>
</net>
<net code="10" name="Net-(J3-Pad2)">
<node ref="J3" pin="2"/>
<node ref="R3" pin="2"/>
</net>
<net code="11" name="Net-(J3-Pad3)">
<node ref="R1" pin="1"/>
<node ref="R2" pin="2"/>
<node ref="J3" pin="3"/>
</net>
<net code="12" name="CLK">
<node ref="U1" pin="B4"/>
<node ref="U1" pin="C4"/>
<node ref="U1" pin="B5"/>
<node ref="U1" pin="C5"/>
<node ref="U3" pin="3"/>
<node ref="J1" pin="4"/>
</net>
<net code="13" name="USB_P">
<node ref="U1" pin="A3"/>
<node ref="J1" pin="2"/>
<node ref="R2" pin="1"/>
</net>
<net code="14" name="USB_N">
<node ref="U1" pin="A4"/>
<node ref="J1" pin="3"/>
<node ref="R3" pin="1"/>
</net>
<net code="15" name="174">
<node ref="J2" pin="6"/>
<node ref="U1" pin="A8"/>
</net>
<net code="16" name="116">
<node ref="U1" pin="A9"/>
<node ref="J2" pin="7"/>
</net>
<net code="17" name="141_GBIN2">
<node ref="U1" pin="E8"/>
<node ref="U1" pin="D7"/>
<node ref="U1" pin="E7"/>
<node ref="J2" pin="8"/>
<node ref="U1" pin="D8"/>
</net>
<net code="18" name="148">
<node ref="J2" pin="9"/>
<node ref="U1" pin="C9"/>
</net>
<net code="19" name="119">
<node ref="U1" pin="D9"/>
<node ref="J2" pin="10"/>
</net>
<net code="20" name="177">
<node ref="U1" pin="A7"/>
<node ref="J2" pin="5"/>
</net>
<net code="21" name="+5V">
<node ref="C1" pin="1"/>
<node ref="J2" pin="1"/>
<node ref="C17" pin="1"/>
<node ref="U2" pin="3"/>
<node ref="U2" pin="1"/>
<node ref="L1" pin="1"/>
</net>
<net code="22" name="185">
<node ref="U1" pin="A6"/>
<node ref="J2" pin="4"/>
</net>
<net code="23" name="Net-(R7-Pad1)">
<node ref="U5" pin="3"/>
<node ref="R7" pin="1"/>
<node ref="TP1" pin="1"/>
</net>
<net code="24" name="3A">
<node ref="J1" pin="8"/>
<node ref="U1" pin="B1"/>
</net>
<net code="25" name="3B">
<node ref="U1" pin="C1"/>
<node ref="J1" pin="9"/>
</net>
<net code="26" name="10A">
<node ref="J1" pin="10"/>
<node ref="U1" pin="D1"/>
</net>
<net code="27" name="24B">
<node ref="J1" pin="12"/>
<node ref="U1" pin="G1"/>
</net>
<net code="28" name="54">
<node ref="J1" pin="13"/>
<node ref="U1" pin="H1"/>
</net>
<net code="29" name="55">
<node ref="J1" pin="14"/>
<node ref="U1" pin="J1"/>
</net>
<net code="30" name="224">
<node ref="U1" pin="A1"/>
<node ref="J1" pin="7"/>
</net>
<net code="31" name="2B">
<node ref="U1" pin="B2"/>
<node ref="J1" pin="5"/>
<node ref="U1" pin="C2"/>
<node ref="U1" pin="C3"/>
<node ref="U1" pin="B3"/>
</net>
<net code="32" name="221">
<node ref="U1" pin="A2"/>
<node ref="J1" pin="6"/>
</net>
<net code="33" name="CRESET_B">
<node ref="SW1" pin="2"/>
<node ref="U1" pin="H5"/>
<node ref="R6" pin="2"/>
<node ref="U1" pin="J4"/>
<node ref="TP2" pin="1"/>
<node ref="U1" pin="H6"/>
</net>
<net code="34" name="VPP_FAST">
<node ref="U1" pin="C7"/>
</net>
<net code="35" name="CDONE">
<node ref="U1" pin="E6"/>
</net>
<net code="36" name="115">
<node ref="U1" pin="D6"/>
</net>
<net code="37" name="10B">
<node ref="J1" pin="11"/>
<node ref="U1" pin="E1"/>
</net>
<net code="38" name="Net-(U1-PadE3)">
<node ref="U1" pin="E3"/>
</net>
<net code="39" name="Net-(U1-PadF3)">
<node ref="U1" pin="F3"/>
</net>
<net code="40" name="GND">
<node ref="C1" pin="2"/>
<node ref="C5" pin="2"/>
<node ref="C9" pin="2"/>
<node ref="C10" pin="2"/>
<node ref="U1" pin="E4"/>
<node ref="C11" pin="2"/>
<node ref="J1" pin="1"/>
<node ref="C2" pin="2"/>
<node ref="C8" pin="2"/>
<node ref="C3" pin="2"/>
<node ref="R7" pin="2"/>
<node ref="C17" pin="2"/>
<node ref="C13" pin="2"/>
<node ref="C16" pin="2"/>
<node ref="C15" pin="2"/>
<node ref="C14" pin="2"/>
<node ref="C4" pin="2"/>
<node ref="J3" pin="5"/>
<node ref="U3" pin="2"/>
<node ref="U5" pin="4"/>
<node ref="U4" pin="2"/>
<node ref="U1" pin="F4"/>
<node ref="SW1" pin="1"/>
<node ref="J3" pin="6"/>
<node ref="U1" pin="F5"/>
<node ref="U1" pin="F6"/>
<node ref="U1" pin="F9"/>
<node ref="U2" pin="2"/>
<node ref="U1" pin="E5"/>
<node ref="C12" pin="2"/>
</net>
<net code="41" name="Net-(U5-Pad7)">
<node ref="U5" pin="7"/>
</net>
<net code="42" name="Net-(J3-Pad4)">
<node ref="J3" pin="4"/>
</net>
<net code="43" name="Net-(U4-Pad4)">
<node ref="U4" pin="4"/>
</net>
<net code="44" name="81_GBIN5">
<node ref="U1" pin="G4"/>
</net>
<net code="45" name="26A">
<node ref="U1" pin="G2"/>
</net>
<net code="46" name="24A">
<node ref="U1" pin="G3"/>
</net>
<net code="47" name="26B">
<node ref="U1" pin="H2"/>
</net>
<net code="48" name="212">
<node ref="U1" pin="D5"/>
</net>
</nets>
</export>

186
board/tinyfpga.lib Normal file
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@@ -0,0 +1,186 @@
EESchema-LIBRARY Version 2.3
DEF MachXO2-1200-QFN32 U 0 40 Y Y 1 L N
F0 "U" 150 250 60 H V R CNN
F1 "MachXO2-1200-QFN32" 150 150 60 H V R CNN
DRAW
X VCCIO3 6 2000 1100 200 D 50 50 1 1 B
X VCCIO2 7 1900 1100 200 D 50 50 1 1 B
X VCCIO2 15 1800 1100 200 D 50 50 1 1 B
X VCC 18 1700 1100 200 D 50 50 1 1 B
X VCCIO1 19 1600 1100 200 D 50 50 1 1 B
X VCCIO0 24 1500 1100 200 D 50 50 1 1 B
X VCCIO0 31 1400 1100 200 D 50 50 1 1 B
X VCC 2 1300 1100 200 D 50 50 1 1 B
X PR5D 20 3200 -1000 200 L 50 50 1 1 B
X PR5C 21 3200 -900 200 L 50 50 1 1 B
X PT17D/DONE 23 3200 -800 200 L 50 50 1 1 B
X PT15D/PROGRAMN 25 3200 -700 200 L 50 50 1 1 B
X PT15C/JTAGENB 26 3200 -600 200 L 50 50 1 1 B
X PT12D/SDA 27 3200 -500 200 L 50 50 1 1 B
X PT12C/SCL 28 3200 -400 200 L 50 50 1 1 B
X PT11D/TMS 29 3200 -300 200 L 50 50 1 1 B
X PT11C/TCK 30 3200 -200 200 L 50 50 1 1 B
X PT10D/TDI 32 3200 -100 200 L 50 50 1 1 B
X PT10C/TDO 1 3200 0 200 L 50 50 1 1 B
X GND 3 1500 -2100 200 U 50 50 1 1 B
X GND 22 1600 -2100 200 U 50 50 1 1 B
X GND 33 1700 -2100 200 U 50 50 1 1 B
X PL9A 4 0 0 200 R 50 50 1 1 B
X PL9B 5 0 -100 200 R 50 50 1 1 B
X PB4C/CS 8 0 -200 200 R 50 50 1 1 B
X PB6C/SCLK 9 0 -300 200 R 50 50 1 1 B
X PB6D/MISO 10 0 -400 200 R 50 50 1 1 B
X PB9A 11 0 -500 200 R 50 50 1 1 B
X PB9B 12 0 -600 200 R 50 50 1 1 B
X PB11A 13 0 -700 200 R 50 50 1 1 B
X PB11B 14 0 -800 200 R 50 50 1 1 B
X PB20C/SN 16 0 -900 200 R 50 50 1 1 B
X PB20D/MOSI 17 0 -1000 200 R 50 50 1 1 B
S 200 900 3000 -1900 1 1 12 N
ENDDRAW
ENDDEF
DEF iCE40-LP8K-CM81 U 0 40 Y Y 8 L N
F0 "U" 200 250 60 H V L CNN
F1 "iCE40-LP8K-CM81" 200 150 60 H V L CNN
DRAW
X VPP_FAST C7 0 0 200 R 50 50 1 1 B
X VPP_2V5 C8 0 -100 200 R 50 50 1 1 B
X CDONE E6 0 -200 200 R 50 50 1 1 B
X IOB_103_CBSEL0 G5 0 -300 200 R 50 50 1 1 B
X IOB_105_SDO G6 0 -400 200 R 50 50 1 1 B
X IOB_107_SCK G7 0 -500 200 R 50 50 1 1 B
X IOB_104_CBSEL1 H5 0 -600 200 R 50 50 1 1 B
X CRESET_B H6 0 -700 200 R 50 50 1 1 B
X IOB_106_SDI H7 0 -800 200 R 50 50 1 1 B
X VCC_SPI H8 0 -900 200 R 50 50 1 1 B
S 200 100 1000 -1000 1 1 12 N
X GND F4 0 0 200 R 50 50 2 1 B
X GND F5 0 -100 200 R 50 50 2 1 B
X GND F6 0 -200 200 R 50 50 2 1 B
X GND F9 0 -300 200 R 50 50 2 1 B
S 200 100 500 -400 2 1 12 N
X IOB_108_SS F7 0 0 200 R 50 50 3 1 B
X IOB_81_GBIN5 G4 0 -100 200 R 50 50 3 1 B
X IOB_54 H1 0 -200 200 R 50 50 3 1 B
X IOB_82_GBIN4 H4 0 -300 200 R 50 50 3 1 B
X IOB_55 J1 0 -400 200 R 50 50 3 1 B
X IOB_56 J2 0 -500 200 R 50 50 3 1 B
X IOB_57 J3 0 -600 200 R 50 50 3 1 B
X IOB_70 J4 0 -700 200 R 50 50 3 1 B
S 200 100 900 -800 3 1 12 N
X IOL_3A B1 0 0 200 R 50 50 4 1 B
X IOL_2B B2 0 -100 200 R 50 50 4 1 B
X IOL_3B C1 0 -200 200 R 50 50 4 1 B
X IOL_2A C2 0 -300 200 R 50 50 4 1 B
X IOL_7B C3 0 -400 200 R 50 50 4 1 B
X IOL_10A D1 0 -500 200 R 50 50 4 1 B
X IOL_7A D2 0 -600 200 R 50 50 4 1 B
X IOL_13B_GBIN7 D3 0 -700 200 R 50 50 4 1 B
X IOL_10B E1 0 -800 200 R 50 50 4 1 B
X IOL_13A E2 0 -900 200 R 50 50 4 1 B
X IOL_14A_GBIN6 E3 0 -1000 200 R 50 50 4 1 B
X IOL_14B E4 0 -1100 200 R 50 50 4 1 B
X IOL_22A F1 0 -1200 200 R 50 50 4 1 B
X IOL_22B F3 0 -1300 200 R 50 50 4 1 B
X IOL_24B G1 0 -1400 200 R 50 50 4 1 B
X IOL_26A G2 0 -1500 200 R 50 50 4 1 B
X IOL_24A G3 0 -1600 200 R 50 50 4 1 B
X IOL_26B H2 0 -1700 200 R 50 50 4 1 B
S 200 100 1000 -1800 4 1 12 N
X IOR_116 A9 0 0 200 R 50 50 5 1 B
X IOR_120 B9 0 -100 200 R 50 50 5 1 B
X IOR_148 C9 0 -200 200 R 50 50 5 1 B
X IOR_115 D6 0 -300 200 R 50 50 5 1 B
X IOR_117 D7 0 -400 200 R 50 50 5 1 B
X IOR_141_GBIN2 D8 0 -500 200 R 50 50 5 1 B
X IOR_119 D9 0 -600 200 R 50 50 5 1 B
X IOR_118 E7 0 -700 200 R 50 50 5 1 B
X IOR_140_GBIN3 E8 0 -800 200 R 50 50 5 1 B
X IOR_113 F8 0 -900 200 R 50 50 5 1 B
X IOR_114 G8 0 -1000 200 R 50 50 5 1 B
X IOR_112 G9 0 -1100 200 R 50 50 5 1 B
X IOR_111 H9 0 -1200 200 R 50 50 5 1 B
X IOR_109 J8 0 -1300 200 R 50 50 5 1 B
X IOR_110 J9 0 -1400 200 R 50 50 5 1 B
S 200 100 1000 -1500 5 1 12 N
X IOT_224 A1 0 0 200 R 50 50 6 1 B
X IOT_221 A2 0 -100 200 R 50 50 6 1 B
X IOT_217 A3 0 -200 200 R 50 50 6 1 B
X IOT_208 A4 0 -300 200 R 50 50 6 1 B
X IOT_185 A6 0 -400 200 R 50 50 6 1 B
X IOT_177 A7 0 -500 200 R 50 50 6 1 B
X IOT_174 A8 0 -600 200 R 50 50 6 1 B
X IOT_218 B3 0 -700 200 R 50 50 6 1 B
X IOT_211 B4 0 -800 200 R 50 50 6 1 B
X IOT_188 B5 0 -900 200 R 50 50 6 1 B
X IOT_183 B6 0 -1000 200 R 50 50 6 1 B
X IOT_180 B7 0 -1100 200 R 50 50 6 1 B
X IOT_170 B8 0 -1200 200 R 50 50 6 1 B
X IOT_198_GBIN0 C4 0 -1300 200 R 50 50 6 1 B
X IOT_197_GBIN1 C5 0 -1400 200 R 50 50 6 1 B
X IOT_212 D5 0 -1500 200 R 50 50 6 1 B
X IOT_214 E5 0 -1600 200 R 50 50 6 1 B
S 200 100 1000 -1700 6 1 12 N
X GNDPLL0 J6 0 0 200 R 50 50 7 1 B
X VCCPLL0 J7 0 -100 200 R 50 50 7 1 B
S 200 100 700 -200 7 1 12 N
X VCCIO_0 A5 0 0 200 R 50 50 8 1 B
X VCCIO_1 C6 0 -100 200 R 50 50 8 1 B
X VCC D4 0 -200 200 R 50 50 8 1 B
X VCC E9 0 -300 200 R 50 50 8 1 B
X VCC F2 0 -400 200 R 50 50 8 1 B
X VCCIO_3 H3 0 -500 200 R 50 50 8 1 B
X VCCIO_2 J5 0 -600 200 R 50 50 8 1 B
S 200 100 700 -700 8 1 12 N
ENDDRAW
ENDDEF
DEF MIC5365-1.2YC5-TR U 0 40 Y Y 1 L N
F0 "U" 200 250 60 H V L CNN
F1 "MIC5365-1.2YC5-TR" 200 150 60 H V L CNN
DRAW
X GND 2 600 -700 200 U 50 50 1 1 B
X VOUT 5 1200 -100 200 L 50 50 1 1 B
X NC 4 1200 0 200 L 50 50 1 1 B
X VIN 1 0 0 200 R 50 50 1 1 B
X EN 3 0 -100 200 R 50 50 1 1 B
S 200 100 1000 -500 1 1 12 N
ENDDRAW
ENDDEF
DEF MIC5504-3.3YM5-TR U 0 40 Y Y 1 L N
F0 "U" 200 250 60 H V L CNN
F1 "MIC5504-3.3YM5-TR" 200 150 60 H V L CNN
DRAW
X GND 2 600 -700 200 U 50 50 1 1 B
X VOUT 5 1200 -100 200 L 50 50 1 1 B
X NC 4 1200 0 200 L 50 50 1 1 B
X VIN 1 0 0 200 R 50 50 1 1 B
X EN 3 0 -100 200 R 50 50 1 1 B
S 200 100 1000 -500 1 1 12 N
ENDDRAW
ENDDEF
DEF DSC6001CI2A-016.0000T U 0 40 Y Y 1 L N
F0 "U" 150 250 60 H V R CNN
F1 "DSC6001CI2A-016.0000T" 150 150 60 H V R CNN
DRAW
X VDD 4 600 600 200 D 50 50 1 1 B
X GND 2 600 -600 200 U 50 50 1 1 B
X OUT 3 1200 0 200 L 50 50 1 1 B
X OE 1 0 0 200 R 50 50 1 1 B
S 200 400 1000 -400 1 1 12 N
ENDDRAW
ENDDEF
DEF AT25SF041-SSHD-B U 0 40 Y Y 1 L N
F0 "U" 150 250 60 H V R CNN
F1 "AT25SF041-SSHD-B" 150 150 60 H V R CNN
DRAW
X VCC 8 700 600 200 D 50 50 1 1 B
X !CS 1 1400 -300 200 L 50 50 1 1 B
X SO 2 1400 -200 200 L 50 50 1 1 B
X SI 5 1400 -100 200 L 50 50 1 1 B
X SCK 6 1400 0 200 L 50 50 1 1 B
X GND 4 700 -900 200 U 50 50 1 1 B
X !WP 3 0 -100 200 R 50 50 1 1 B
X !HOLD 7 0 -200 200 R 50 50 1 1 B
S 200 400 1200 -700 1 1 12 N
ENDDRAW
ENDDEF

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(module CDFN3225-4LD-PL-1 (layer F.Cu) (tedit 591AA274)
(fp_text reference REF** (at 0 3.05) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value CDFN3225-4LD-PL-1 (at 0 -2.85) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_circle (center -2.361386 1.541754) (end -2.161386 1.391754) (layer F.Fab) (width 0.15))
(fp_line (start 1.438614 1.041754) (end -1.761386 1.041754) (layer F.Fab) (width 0.15))
(fp_line (start 1.438614 -1.458246) (end 1.438614 1.041754) (layer F.Fab) (width 0.15))
(fp_line (start -1.761386 -1.458246) (end 1.438614 -1.458246) (layer F.Fab) (width 0.15))
(fp_line (start -1.761386 1.041754) (end -1.761386 -1.458246) (layer F.Fab) (width 0.15))
(pad 1 smd rect (at -1.211386 0.741754 90) (size 1 0.9) (layers F.Cu F.Paste F.Mask))
(pad 4 smd rect (at -1.211386 -1.158246 90) (size 1 0.9) (layers F.Cu F.Paste F.Mask))
(pad 3 smd rect (at 0.888614 -1.158246 90) (size 1 0.9) (layers F.Cu F.Paste F.Mask))
(pad 2 smd rect (at 0.888614 0.741754 90) (size 1 0.9) (layers F.Cu F.Paste F.Mask))
)

View File

@@ -0,0 +1,94 @@
(module CM81 (layer F.Cu) (tedit 5902DC62)
(clearance 0.102)
(fp_text reference REF** (at 1.6 6.4) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value CM81 (at 1.6 0.8) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -0.4 2.4) (end -0.4 5.6) (layer F.SilkS) (width 0.15))
(fp_line (start -0.4 5.6) (end 3.6 5.6) (layer F.SilkS) (width 0.15))
(fp_line (start 3.6 5.6) (end 3.6 1.6) (layer F.SilkS) (width 0.15))
(fp_line (start 3.6 1.6) (end 0.4 1.6) (layer F.SilkS) (width 0.15))
(pad A1 smd circle (at 0 2) (size 0.2 0.2) (layers F.Cu F.Paste F.Mask))
(pad A2 smd circle (at 0.4 2) (size 0.2 0.2) (layers F.Cu F.Paste F.Mask))
(pad A3 smd circle (at 0.8 2) (size 0.2 0.2) (layers F.Cu F.Paste F.Mask))
(pad A4 smd circle (at 1.2 2) (size 0.2 0.2) (layers F.Cu F.Paste F.Mask))
(pad A5 smd circle (at 1.6 2) (size 0.2 0.2) (layers F.Cu F.Paste F.Mask))
(pad A6 smd circle (at 2 2) (size 0.2 0.2) (layers F.Cu F.Paste F.Mask))
(pad A7 smd circle (at 2.4 2) (size 0.2 0.2) (layers F.Cu F.Paste F.Mask))
(pad A8 smd circle (at 2.8 2) (size 0.2 0.2) (layers F.Cu F.Paste F.Mask))
(pad A9 smd circle (at 3.2 2) (size 0.2 0.2) (layers F.Cu F.Paste F.Mask))
(pad B1 smd circle (at 0 2.4) (size 0.2 0.2) (layers F.Cu F.Paste F.Mask))
(pad B2 smd circle (at 0.4 2.4) (size 0.2 0.2) (layers F.Cu F.Paste F.Mask))
(pad B3 smd circle (at 0.8 2.4) (size 0.2 0.2) (layers F.Cu F.Paste F.Mask))
(pad B4 smd circle (at 1.2 2.4) (size 0.2 0.2) (layers F.Cu F.Paste F.Mask))
(pad B5 smd circle (at 1.6 2.4) (size 0.2 0.2) (layers F.Cu F.Paste F.Mask))
(pad B6 smd circle (at 2 2.4) (size 0.2 0.2) (layers F.Cu F.Paste F.Mask))
(pad B7 smd circle (at 2.4 2.4) (size 0.2 0.2) (layers F.Cu F.Paste F.Mask))
(pad B8 smd circle (at 2.8 2.4) (size 0.2 0.2) (layers F.Cu F.Paste F.Mask))
(pad B9 smd circle (at 3.2 2.4) (size 0.2 0.2) (layers F.Cu F.Paste F.Mask))
(pad C1 smd circle (at 0 2.8) (size 0.2 0.2) (layers F.Cu F.Paste F.Mask))
(pad C2 smd circle (at 0.4 2.8) (size 0.2 0.2) (layers F.Cu F.Paste F.Mask))
(pad C3 smd circle (at 0.8 2.8) (size 0.2 0.2) (layers F.Cu F.Paste F.Mask))
(pad C4 smd circle (at 1.2 2.8) (size 0.2 0.2) (layers F.Cu F.Paste F.Mask))
(pad C5 smd circle (at 1.6 2.8) (size 0.2 0.2) (layers F.Cu F.Paste F.Mask))
(pad C6 smd circle (at 2 2.8) (size 0.2 0.2) (layers F.Cu F.Paste F.Mask))
(pad C7 smd circle (at 2.4 2.8) (size 0.2 0.2) (layers F.Cu F.Paste F.Mask))
(pad C8 smd circle (at 2.8 2.8) (size 0.2 0.2) (layers F.Cu F.Paste F.Mask))
(pad C9 smd circle (at 3.2 2.8) (size 0.2 0.2) (layers F.Cu F.Paste F.Mask))
(pad D1 smd circle (at 0 3.2) (size 0.2 0.2) (layers F.Cu F.Paste F.Mask))
(pad D2 smd circle (at 0.4 3.2) (size 0.2 0.2) (layers F.Cu F.Paste F.Mask))
(pad D3 smd circle (at 0.8 3.2) (size 0.2 0.2) (layers F.Cu F.Paste F.Mask))
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View File

@@ -0,0 +1,136 @@
#VRML V2.0 utf8
#kicad StepUp wrl exported
# Copyright (C) 2017, kicad StepUp
#
# This program is free software: you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation, either version 3 of the License, or
# any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program. If not, see http://www.gnu.org/licenses/.
#
# As a special exception, if you create a design which uses this symbol,
# and embed this symbol or unaltered portions of this symbol into the design,
# this symbol does not by itself cause the resulting design to be covered by
# the GNU General Public License.
# This exception does not however invalidate any other reasons why the design
# itself might be covered by the GNU General Public License.
# If you modify this symbol, you may extend this exception to your version of the symbol,
# but you are not obligated to do so.
# If you do not wish to do so, delete this exception statement from your version
# Risk disclaimer
# *USE 3D CAD DATA AT YOUR OWN RISK*
# *DO NOT RELY UPON ANY INFORMATION FOUND HERE WITHOUT INDEPENDENT VERIFICATION.*
#
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transparency 0.0
shininess 0.7
}
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emissiveColor 0.0 0.0 0.0
transparency 0.0
shininess 0.01
}
}
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View File

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#VRML V2.0 utf8
#kicad StepUp wrl exported
# Copyright (C) 2017, kicad StepUp
#
# This program is free software: you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation, either version 3 of the License, or
# any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program. If not, see http://www.gnu.org/licenses/.
#
# As a special exception, if you create a design which uses this symbol,
# and embed this symbol or unaltered portions of this symbol into the design,
# this symbol does not by itself cause the resulting design to be covered by
# the GNU General Public License.
# This exception does not however invalidate any other reasons why the design
# itself might be covered by the GNU General Public License.
# If you modify this symbol, you may extend this exception to your version of the symbol,
# but you are not obligated to do so.
# If you do not wish to do so, delete this exception statement from your version
# Risk disclaimer
# *USE 3D CAD DATA AT YOUR OWN RISK*
# *DO NOT RELY UPON ANY INFORMATION FOUND HERE WITHOUT INDEPENDENT VERIFICATION.*
#
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diffuseColor 0.824 0.82 0.781
specularColor 0.328 0.258 0.172
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transparency 0.0
shininess 0.01
}
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appearance Appearance{material USE PIN-01 }
}
Shape { geometry IndexedFaceSet
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}}
appearance Appearance{material USE PIN-01 }
}
Shape { geometry IndexedFaceSet
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appearance Appearance{material USE PIN-01 }
}
Shape { geometry IndexedFaceSet
{ creaseAngle 0.50 coordIndex [0,1,2,-1,0,3,1,-1,4,5,0,-1,4,6,5,-1,7,2,8,-1,7,8,9,-1,10,11,4,-1,10,4,0,-1,12,7,13,-1,12,0,2,-1,12,2,7,-1,12,10,0,-1,14,10,12,-1]
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}}
appearance Appearance{material USE PIN-01 }
}
Shape { geometry IndexedFaceSet
{ creaseAngle 0.50 coordIndex [0,1,2,-1,3,0,2,-1]
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}}
appearance Appearance{material USE PIN-01 }
}
Shape { geometry IndexedFaceSet
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appearance Appearance{material USE PIN-01 }
}
Shape { geometry IndexedFaceSet
{ creaseAngle 0.50 coordIndex [0,1,2,-1,2,1,3,-1]
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appearance Appearance{material USE PIN-01 }
}
Shape { geometry IndexedFaceSet
{ creaseAngle 0.50 coordIndex [0,1,2,-1,3,4,5,-1,3,6,4,-1,3,5,7,-1,8,2,6,-1,8,9,0,-1,8,10,9,-1,8,11,10,-1,8,3,12,-1,8,0,2,-1,8,6,3,-1,13,8,12,-1,14,8,13,-1]
coord Coordinate { point [0.638 -0.128 0.000,0.647 -0.116 0.000,0.659 -0.106 0.000,0.689 -0.217 0.000,0.689 -0.098 0.000,0.787 -0.098 0.000,0.674 -0.100 0.000,0.787 -0.217 0.000,0.638 -0.187 0.000,0.632 -0.142 0.000,0.630 -0.157 0.000,0.632 -0.173 0.000,0.674 -0.215 0.000,0.659 -0.209 0.000,0.647 -0.199 0.000]
}}
appearance Appearance{material USE PIN-01 }
}
Shape { geometry IndexedFaceSet
{ creaseAngle 0.50 coordIndex [0,1,2,-1,2,1,3,-1]
coord Coordinate { point [0.787 -0.217 0.079,0.787 -0.217 0.000,0.787 -0.098 0.079,0.787 -0.098 0.000]
}}
appearance Appearance{material USE PIN-01 }
}
Shape { geometry IndexedFaceSet
{ creaseAngle 0.50 coordIndex [0,1,2,-1,0,3,1,-1,4,5,0,-1,4,6,5,-1,7,2,8,-1,7,8,9,-1,10,11,4,-1,10,4,0,-1,12,7,13,-1,12,0,2,-1,12,2,7,-1,12,10,0,-1,14,10,12,-1]
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appearance Appearance{material USE PIN-01 }
}
Shape { geometry IndexedFaceSet
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appearance Appearance{material USE PIN-01 }
}
Shape { geometry IndexedFaceSet
{ creaseAngle 0.50 coordIndex [0,1,2,-1,3,4,5,-1,3,6,4,-1,3,5,7,-1,8,2,6,-1,8,9,0,-1,8,10,9,-1,8,11,10,-1,8,3,12,-1,8,6,3,-1,8,0,2,-1,13,8,12,-1,14,8,13,-1]
coord Coordinate { point [0.638 -0.443 0.000,0.647 -0.431 0.000,0.659 -0.421 0.000,0.689 -0.531 0.000,0.689 -0.413 0.000,0.787 -0.413 0.000,0.674 -0.415 0.000,0.787 -0.531 0.000,0.638 -0.502 0.000,0.632 -0.457 0.000,0.630 -0.472 0.000,0.632 -0.488 0.000,0.674 -0.529 0.000,0.659 -0.524 0.000,0.647 -0.514 0.000]
}}
appearance Appearance{material USE PIN-01 }
}
Shape { geometry IndexedFaceSet
{ creaseAngle 0.50 coordIndex [0,1,2,-1,3,0,2,-1]
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}}
appearance Appearance{material USE PIN-01 }
}
Shape { geometry IndexedFaceSet
{ creaseAngle 0.50 coordIndex [0,1,2,-1,0,3,1,-1,4,5,0,-1,4,6,5,-1,7,2,8,-1,7,8,9,-1,10,11,4,-1,10,4,0,-1,12,7,13,-1,12,0,2,-1,12,2,7,-1,12,10,0,-1,14,10,12,-1]
coord Coordinate { point [-0.647 -0.514 0.000,-0.674 -0.529 0.000,-0.689 -0.531 0.000,-0.659 -0.524 0.000,-0.630 -0.472 0.000,-0.638 -0.502 0.000,-0.632 -0.488 0.000,-0.689 -0.413 0.000,-0.787 -0.531 0.000,-0.787 -0.413 0.000,-0.638 -0.443 0.000,-0.632 -0.457 0.000,-0.659 -0.421 0.000,-0.674 -0.415 0.000,-0.647 -0.431 0.000]
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appearance Appearance{material USE PIN-01 }
}
Shape { geometry IndexedFaceSet
{ creaseAngle 0.50 coordIndex [0,1,2,-1,3,0,2,-1]
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appearance Appearance{material USE PIN-01 }
}
Shape { geometry IndexedFaceSet
{ creaseAngle 0.50 coordIndex [0,1,2,-1,3,1,0,-1,4,3,0,-1]
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appearance Appearance{material USE PIN-01 }
}
Shape { geometry IndexedFaceSet
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appearance Appearance{material USE IC-LABEL-01 }
}
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{ creaseAngle 0.50 coordIndex [0,1,2,-1,3,4,5,-1,3,5,1,-1,3,0,6,-1,3,1,0,-1,7,4,3,-1,8,9,4,-1,10,11,8,-1,12,7,13,-1,12,13,14,-1,12,8,4,-1,12,4,7,-1,12,10,8,-1,15,16,10,-1,15,10,12,-1,17,12,18,-1,17,15,12,-1,19,20,15,-1,19,15,17,-1,21,20,19,-1,22,21,19,-1,23,24,21,-1,23,21,22,-1]
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appearance Appearance{material USE IC-LABEL-01 }
}

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@@ -0,0 +1,87 @@
(module Lattice-32QFN (layer F.Cu) (tedit 59058BFE)
(fp_text reference REF** (at 0.1 4.75) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value Lattice-32QFN (at 0.05 -4.8) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -2.5 -1.5) (end -1.5 -2.5) (layer F.Fab) (width 0.15))
(fp_line (start -2.5 2.5) (end -2.5 -1.5) (layer F.Fab) (width 0.15))
(fp_line (start 2.5 2.5) (end -2.5 2.5) (layer F.Fab) (width 0.15))
(fp_line (start 2.5 -2.5) (end 2.5 2.5) (layer F.Fab) (width 0.15))
(fp_line (start -1.5 -2.5) (end 2.5 -2.5) (layer F.Fab) (width 0.15))
(fp_line (start -1.25 0) (end 1.25 0) (layer F.Mask) (width 0.3))
(fp_line (start -1.35 1.35) (end -1.35 -1.35) (layer F.Mask) (width 0.15))
(fp_line (start 1.35 1.35) (end -1.35 1.35) (layer F.Mask) (width 0.15))
(fp_line (start 1.35 -1.35) (end 1.35 1.35) (layer F.Mask) (width 0.15))
(fp_line (start -1.35 -1.35) (end 1.35 -1.35) (layer F.Mask) (width 0.15))
(fp_line (start 0 -1.25) (end 0 1.25) (layer F.Mask) (width 0.3))
(pad 32 smd oval (at -1.75 -2.5 90) (size 0.7 0.24) (layers F.Cu F.Paste F.Mask)
(solder_mask_margin 0.07))
(pad 31 smd oval (at -1.25 -2.5 90) (size 0.7 0.24) (layers F.Cu F.Paste F.Mask)
(solder_mask_margin 0.07))
(pad 30 smd oval (at -0.75 -2.5 90) (size 0.7 0.24) (layers F.Cu F.Paste F.Mask)
(solder_mask_margin 0.07))
(pad 29 smd oval (at -0.25 -2.5 90) (size 0.7 0.24) (layers F.Cu F.Paste F.Mask)
(solder_mask_margin 0.07))
(pad 28 smd oval (at 0.25 -2.5 90) (size 0.7 0.24) (layers F.Cu F.Paste F.Mask)
(solder_mask_margin 0.07))
(pad 27 smd oval (at 0.75 -2.5 90) (size 0.7 0.24) (layers F.Cu F.Paste F.Mask)
(solder_mask_margin 0.07))
(pad 26 smd oval (at 1.25 -2.5 90) (size 0.7 0.24) (layers F.Cu F.Paste F.Mask)
(solder_mask_margin 0.07))
(pad 25 smd oval (at 1.75 -2.5 90) (size 0.7 0.24) (layers F.Cu F.Paste F.Mask)
(solder_mask_margin 0.07))
(pad 24 smd oval (at 2.5 -1.75) (size 0.7 0.24) (layers F.Cu F.Paste F.Mask)
(solder_mask_margin 0.07))
(pad 23 smd oval (at 2.5 -1.25) (size 0.7 0.24) (layers F.Cu F.Paste F.Mask)
(solder_mask_margin 0.07))
(pad 22 smd oval (at 2.5 -0.75) (size 0.7 0.24) (layers F.Cu F.Paste F.Mask)
(solder_mask_margin 0.07))
(pad 21 smd oval (at 2.5 -0.25) (size 0.7 0.24) (layers F.Cu F.Paste F.Mask)
(solder_mask_margin 0.07))
(pad 20 smd oval (at 2.5 0.25) (size 0.7 0.24) (layers F.Cu F.Paste F.Mask)
(solder_mask_margin 0.07))
(pad 19 smd oval (at 2.5 0.75) (size 0.7 0.24) (layers F.Cu F.Paste F.Mask)
(solder_mask_margin 0.07))
(pad 18 smd oval (at 2.5 1.25) (size 0.7 0.24) (layers F.Cu F.Paste F.Mask)
(solder_mask_margin 0.07))
(pad 17 smd oval (at 2.5 1.75) (size 0.7 0.24) (layers F.Cu F.Paste F.Mask)
(solder_mask_margin 0.07))
(pad 16 smd oval (at 1.75 2.5 90) (size 0.7 0.24) (layers F.Cu F.Paste F.Mask)
(solder_mask_margin 0.07))
(pad 15 smd oval (at 1.25 2.5 90) (size 0.7 0.24) (layers F.Cu F.Paste F.Mask)
(solder_mask_margin 0.07))
(pad 14 smd oval (at 0.75 2.5 90) (size 0.7 0.24) (layers F.Cu F.Paste F.Mask)
(solder_mask_margin 0.07))
(pad 13 smd oval (at 0.25 2.5 90) (size 0.7 0.24) (layers F.Cu F.Paste F.Mask)
(solder_mask_margin 0.07))
(pad 12 smd oval (at -0.25 2.5 90) (size 0.7 0.24) (layers F.Cu F.Paste F.Mask)
(solder_mask_margin 0.07))
(pad 11 smd oval (at -0.75 2.5 90) (size 0.7 0.24) (layers F.Cu F.Paste F.Mask)
(solder_mask_margin 0.07))
(pad 10 smd oval (at -1.25 2.5 90) (size 0.7 0.24) (layers F.Cu F.Paste F.Mask)
(solder_mask_margin 0.07))
(pad 9 smd oval (at -1.75 2.5 90) (size 0.7 0.24) (layers F.Cu F.Paste F.Mask)
(solder_mask_margin 0.07))
(pad 8 smd oval (at -2.5 1.75) (size 0.7 0.24) (layers F.Cu F.Paste F.Mask)
(solder_mask_margin 0.07))
(pad 7 smd oval (at -2.5 1.25) (size 0.7 0.24) (layers F.Cu F.Paste F.Mask)
(solder_mask_margin 0.07))
(pad 6 smd oval (at -2.5 0.75) (size 0.7 0.24) (layers F.Cu F.Paste F.Mask)
(solder_mask_margin 0.07))
(pad 5 smd oval (at -2.5 0.25) (size 0.7 0.24) (layers F.Cu F.Paste F.Mask)
(solder_mask_margin 0.07))
(pad 4 smd oval (at -2.5 -0.25) (size 0.7 0.24) (layers F.Cu F.Paste F.Mask)
(solder_mask_margin 0.07))
(pad 3 smd oval (at -2.5 -0.75) (size 0.7 0.24) (layers F.Cu F.Paste F.Mask)
(solder_mask_margin 0.07))
(pad 2 smd oval (at -2.5 -1.25) (size 0.7 0.24) (layers F.Cu F.Paste F.Mask)
(solder_mask_margin 0.07))
(pad 1 smd oval (at -2.5 -1.75) (size 0.7 0.24) (layers F.Cu F.Paste F.Mask)
(solder_mask_margin 0.07))
(pad 33 smd rect (at -0.7 -0.7) (size 1.17 1.17) (layers F.Cu F.Paste F.Mask))
(pad 33 smd rect (at 0.7 0.7) (size 1.17 1.17) (layers F.Cu F.Paste F.Mask))
(pad 33 smd rect (at 0.7 -0.7) (size 1.17 1.17) (layers F.Cu F.Paste F.Mask))
(pad 33 smd rect (at -0.7 0.7) (size 1.17 1.17) (layers F.Cu F.Paste F.Mask))
)

View File

@@ -0,0 +1,72 @@
(module Lattice-QFN-32_5x5mm_Pitch0.5mm locked (layer F.Cu) (tedit 59043BB9)
(descr "UH Package; 32-Lead Plastic QFN (5mm x 5mm); (see Linear Technology QFN_32_05-08-1693.pdf)")
(tags "QFN 0.5")
(attr smd)
(fp_text reference U2 (at 0 -3.75) (layer F.SilkS) hide
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value MachXO2-1200-QFN32 (at 0 3.75) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -1.5 -2.5) (end 2.5 -2.5) (layer F.Fab) (width 0.15))
(fp_line (start 2.5 -2.5) (end 2.5 2.5) (layer F.Fab) (width 0.15))
(fp_line (start 2.5 2.5) (end -2.5 2.5) (layer F.Fab) (width 0.15))
(fp_line (start -2.5 2.5) (end -2.5 -1.5) (layer F.Fab) (width 0.15))
(fp_line (start -2.5 -1.5) (end -1.5 -2.5) (layer F.Fab) (width 0.15))
(fp_line (start -3 -3) (end -3 3) (layer F.CrtYd) (width 0.05))
(fp_line (start 3 -3) (end 3 3) (layer F.CrtYd) (width 0.05))
(fp_line (start -3 -3) (end 3 -3) (layer F.CrtYd) (width 0.05))
(fp_line (start -3 3) (end 3 3) (layer F.CrtYd) (width 0.05))
(fp_line (start 2.625 -2.625) (end 2.625 -2.1) (layer F.SilkS) (width 0.15))
(fp_line (start -2.625 2.625) (end -2.625 2.1) (layer F.SilkS) (width 0.15))
(fp_line (start 2.625 2.625) (end 2.625 2.1) (layer F.SilkS) (width 0.15))
(fp_line (start -2.625 -2.625) (end -2.1 -2.625) (layer F.SilkS) (width 0.15))
(fp_line (start -2.625 2.625) (end -2.1 2.625) (layer F.SilkS) (width 0.15))
(fp_line (start 2.625 2.625) (end 2.1 2.625) (layer F.SilkS) (width 0.15))
(fp_line (start 2.625 -2.625) (end 2.1 -2.625) (layer F.SilkS) (width 0.15))
(pad 1 smd rect (at -2.4 -1.75) (size 0.7 0.25) (layers F.Cu F.Paste F.Mask))
(pad 2 smd rect (at -2.4 -1.25) (size 0.7 0.25) (layers F.Cu F.Paste F.Mask))
(pad 3 smd rect (at -2.4 -0.75) (size 0.7 0.25) (layers F.Cu F.Paste F.Mask))
(pad 4 smd rect (at -2.4 -0.25) (size 0.7 0.25) (layers F.Cu F.Paste F.Mask))
(pad 5 smd rect (at -2.4 0.25) (size 0.7 0.25) (layers F.Cu F.Paste F.Mask))
(pad 6 smd rect (at -2.4 0.75) (size 0.7 0.25) (layers F.Cu F.Paste F.Mask))
(pad 7 smd rect (at -2.4 1.25) (size 0.7 0.25) (layers F.Cu F.Paste F.Mask))
(pad 8 smd rect (at -2.4 1.75) (size 0.7 0.25) (layers F.Cu F.Paste F.Mask))
(pad 9 smd rect (at -1.75 2.4 90) (size 0.7 0.25) (layers F.Cu F.Paste F.Mask))
(pad 10 smd rect (at -1.25 2.4 90) (size 0.7 0.25) (layers F.Cu F.Paste F.Mask))
(pad 11 smd rect (at -0.75 2.4 90) (size 0.7 0.25) (layers F.Cu F.Paste F.Mask))
(pad 12 smd rect (at -0.25 2.4 90) (size 0.7 0.25) (layers F.Cu F.Paste F.Mask))
(pad 13 smd rect (at 0.25 2.4 90) (size 0.7 0.25) (layers F.Cu F.Paste F.Mask))
(pad 14 smd rect (at 0.75 2.4 90) (size 0.7 0.25) (layers F.Cu F.Paste F.Mask))
(pad 15 smd rect (at 1.25 2.4 90) (size 0.7 0.25) (layers F.Cu F.Paste F.Mask))
(pad 16 smd rect (at 1.75 2.4 90) (size 0.7 0.25) (layers F.Cu F.Paste F.Mask))
(pad 17 smd rect (at 2.4 1.75) (size 0.7 0.25) (layers F.Cu F.Paste F.Mask))
(pad 18 smd rect (at 2.4 1.25) (size 0.7 0.25) (layers F.Cu F.Paste F.Mask))
(pad 19 smd rect (at 2.4 0.75) (size 0.7 0.25) (layers F.Cu F.Paste F.Mask))
(pad 20 smd rect (at 2.4 0.25) (size 0.7 0.25) (layers F.Cu F.Paste F.Mask))
(pad 21 smd rect (at 2.4 -0.25) (size 0.7 0.25) (layers F.Cu F.Paste F.Mask))
(pad 22 smd rect (at 2.4 -0.75) (size 0.7 0.25) (layers F.Cu F.Paste F.Mask))
(pad 23 smd rect (at 2.4 -1.25) (size 0.7 0.25) (layers F.Cu F.Paste F.Mask))
(pad 24 smd rect (at 2.4 -1.75) (size 0.7 0.25) (layers F.Cu F.Paste F.Mask))
(pad 25 smd rect (at 1.75 -2.4 90) (size 0.7 0.25) (layers F.Cu F.Paste F.Mask))
(pad 26 smd rect (at 1.25 -2.4 90) (size 0.7 0.25) (layers F.Cu F.Paste F.Mask))
(pad 27 smd rect (at 0.75 -2.4 90) (size 0.7 0.25) (layers F.Cu F.Paste F.Mask))
(pad 28 smd rect (at 0.25 -2.4 90) (size 0.7 0.25) (layers F.Cu F.Paste F.Mask))
(pad 29 smd rect (at -0.25 -2.4 90) (size 0.7 0.25) (layers F.Cu F.Paste F.Mask))
(pad 30 smd rect (at -0.75 -2.4 90) (size 0.7 0.25) (layers F.Cu F.Paste F.Mask))
(pad 31 smd rect (at -1.25 -2.4 90) (size 0.7 0.25) (layers F.Cu F.Paste F.Mask))
(pad 32 smd rect (at -1.75 -2.4 90) (size 0.7 0.25) (layers F.Cu F.Paste F.Mask))
(pad 33 smd rect (at 0.8625 0.8625) (size 1.725 1.725) (layers F.Cu F.Paste F.Mask)
(solder_paste_margin_ratio -0.2))
(pad 33 smd rect (at 0.8625 -0.8625) (size 1.725 1.725) (layers F.Cu F.Paste F.Mask)
(solder_paste_margin_ratio -0.2))
(pad 33 smd rect (at -0.8625 0.8625) (size 1.725 1.725) (layers F.Cu F.Paste F.Mask)
(solder_paste_margin_ratio -0.2))
(pad 33 smd rect (at -0.8625 -0.8625) (size 1.725 1.725) (layers F.Cu F.Paste F.Mask)
(solder_paste_margin_ratio -0.2))
(model Housings_DFN_QFN.3dshapes/QFN-32-1EP_5x5mm_Pitch0.5mm.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)

View File

@@ -0,0 +1,17 @@
(module PTS_810_SMT_Switch (layer F.Cu) (tedit 591A91F4)
(fp_text reference REF** (at 0 3.2) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value "PTS 810 SMT Switch" (at 0 -3) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 2.1 -1.6) (end -2.1 -1.6) (layer F.Fab) (width 0.15))
(fp_line (start 2.1 1.6) (end 2.1 -1.6) (layer F.Fab) (width 0.15))
(fp_line (start -2.1 1.6) (end 2.1 1.6) (layer F.Fab) (width 0.15))
(fp_line (start -2.1 1.2) (end -2.1 1.6) (layer F.Fab) (width 0.15))
(fp_line (start -2.1 -1.6) (end -2.1 1.2) (layer F.Fab) (width 0.15))
(pad 1 smd rect (at -2.075 -1.075) (size 1.05 0.65) (layers F.Cu F.Paste F.Mask))
(pad 1 smd rect (at 2.075 -1.075) (size 1.05 0.65) (layers F.Cu F.Paste F.Mask))
(pad 2 smd rect (at 2.075 1.075) (size 1.05 0.65) (layers F.Cu F.Paste F.Mask))
(pad 2 smd rect (at -2.075 1.075) (size 1.05 0.65) (layers F.Cu F.Paste F.Mask))
)

View File

File diff suppressed because one or more lines are too long

View File

@@ -0,0 +1,18 @@
(module SC-70-C5 (layer F.Cu) (tedit 591AA024)
(fp_text reference REF** (at 0 2.85) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value SC-70-C5 (at 0 -2.85) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_circle (center 1.4 -1) (end 1.6 -0.925) (layer F.Fab) (width 0.15))
(fp_line (start 1 -0.625) (end 1 0.625) (layer F.Fab) (width 0.15))
(fp_line (start -1 -0.625) (end -1 0.625) (layer F.Fab) (width 0.15))
(fp_line (start 1 0.625) (end -1 0.625) (layer F.Fab) (width 0.15))
(fp_line (start 1 -0.625) (end -1 -0.625) (layer F.Fab) (width 0.15))
(pad 2 smd rect (at 0 -1.1) (size 0.45 0.95) (layers F.Cu F.Paste F.Mask))
(pad 3 smd rect (at -0.65 -1.1) (size 0.45 0.95) (layers F.Cu F.Paste F.Mask))
(pad 1 smd rect (at 0.65 -1.1) (size 0.45 0.95) (layers F.Cu F.Paste F.Mask))
(pad 4 smd rect (at -0.65 1.1) (size 0.45 0.95) (layers F.Cu F.Paste F.Mask))
(pad 5 smd rect (at 0.65 1.1) (size 0.45 0.95) (layers F.Cu F.Paste F.Mask))
)

View File

@@ -0,0 +1,705 @@
#VRML V2.0 utf8
#kicad StepUp wrl exported
# Copyright (C) 2017, kicad StepUp
#
# This work is licensed under the [Creative Commons CC-BY-SA 4.0 License](https://creativecommons.org/licenses/by-sa/4.0/legalcode),
# with the following exception:
# To the extent that the creation of electronic designs that use 'Licensed Material' can be considered to be 'Adapted Material',
# then the copyright holder waives article 3 of the license with respect to these designs and any generated files which use data provided
# as part of the 'Licensed Material'.
# You are free to use the library data in your own projects without the obligation to share your project files under this or any other license agreement.
# However, if you wish to redistribute these libraries, or parts thereof (including in modified form) as a collection then the exception above does not apply.
# Please refer to https://github.com/KiCad/kicad-packages3D/blob/master/LICENSE.md for further clarification of the exception.
# Disclaimer of Warranties and Limitation of Liability.
# These libraries are provided in the hope that they will be useful, but are provided without warranty of any kind, express or implied.
# *USE 3D CAD DATA AT YOUR OWN RISK*
# *DO NOT RELY UPON ANY INFORMATION FOUND HERE WITHOUT INDEPENDENT VERIFICATION.*
#
Shape {
appearance Appearance {material DEF PIN-01 Material {
ambientIntensity 0.271
diffuseColor 0.824 0.82 0.781
specularColor 0.328 0.258 0.172
emissiveColor 0.0 0.0 0.0
transparency 0.0
shininess 0.7
}
}
}
Shape {
appearance Appearance {material DEF IC-LABEL-01 Material {
ambientIntensity 0.082
diffuseColor 0.691 0.664 0.598
specularColor 0.0 0.0 0.0
emissiveColor 0.0 0.0 0.0
transparency 0.0
shininess 0.01
}
}
}
Shape {
appearance Appearance {material DEF IC-BODY-EPOXY-04 Material {
ambientIntensity 0.293
diffuseColor 0.148 0.145 0.145
specularColor 0.18 0.168 0.16
emissiveColor 0.0 0.0 0.0
transparency 0.0
shininess 0.35
}
}
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}}
appearance Appearance{material USE IC-BODY-EPOXY-04 }
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appearance Appearance{material USE IC-BODY-EPOXY-04 }
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appearance Appearance{material USE IC-BODY-EPOXY-04 }
}
Shape { geometry IndexedFaceSet
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appearance Appearance{material USE IC-BODY-EPOXY-04 }
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Shape { geometry IndexedFaceSet
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coord Coordinate { point [-0.282 0.524 0.091,-0.277 0.528 0.091,-0.279 0.515 0.039,-0.272 0.533 0.091,-0.260 0.535 0.039,-0.268 0.537 0.091,-0.288 0.528 0.142,-0.283 0.533 0.142,-0.277 0.539 0.142,-0.272 0.544 0.142,-0.315 0.533 0.295,-0.295 0.532 0.193,-0.288 0.538 0.193,-0.282 0.544 0.193,-0.276 0.550 0.193,-0.278 0.571 0.295,-0.301 0.537 0.244,-0.294 0.543 0.244,-0.287 0.550 0.244,-0.281 0.557 0.244]
}}
appearance Appearance{material USE IC-BODY-EPOXY-04 }
}
Shape { geometry IndexedFaceSet
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}}
appearance Appearance{material USE IC-BODY-EPOXY-04 }
}
Shape { geometry IndexedFaceSet
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}}
appearance Appearance{material USE IC-BODY-EPOXY-04 }
}
Shape { geometry IndexedFaceSet
{ creaseAngle 0.50 coordIndex [0,1,2,-1,3,1,0,-1]
coord Coordinate { point [0.260 -0.535 0.039,-0.278 -0.571 0.295,-0.260 -0.535 0.039,0.278 -0.571 0.295]
}}
appearance Appearance{material USE IC-BODY-EPOXY-04 }
}
Shape { geometry IndexedFaceSet
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appearance Appearance{material USE IC-BODY-EPOXY-04 }
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appearance Appearance{material USE IC-BODY-EPOXY-04 }
}
Shape { geometry IndexedFaceSet
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appearance Appearance{material USE IC-BODY-EPOXY-04 }
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Shape { geometry IndexedFaceSet
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appearance Appearance{material USE IC-BODY-EPOXY-04 }
}
Shape { geometry IndexedFaceSet
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coord Coordinate { point [-0.315 0.533 0.295,-0.278 0.571 0.354,-0.278 0.571 0.295,-0.315 0.533 0.354]
}}
appearance Appearance{material USE IC-BODY-EPOXY-04 }
}
Shape { geometry IndexedFaceSet
{ creaseAngle 0.50 coordIndex [0,1,2,-1,2,1,3,-1]
coord Coordinate { point [0.315 0.533 0.354,0.315 0.472 0.354,0.315 0.533 0.295,0.315 0.472 0.295]
}}
appearance Appearance{material USE IC-BODY-EPOXY-04 }
}
Shape { geometry IndexedFaceSet
{ creaseAngle 0.50 coordIndex [0,1,2,-1,2,1,3,-1]
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}}
appearance Appearance{material USE IC-BODY-EPOXY-04 }
}
Shape { geometry IndexedFaceSet
{ creaseAngle 0.50 coordIndex [0,1,2,-1,3,1,0,-1]
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appearance Appearance{material USE PIN-01 }
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Shape { geometry IndexedFaceSet
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appearance Appearance{material USE PIN-01 }
}
Shape { geometry IndexedFaceSet
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appearance Appearance{material USE IC-BODY-EPOXY-04 }
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Shape { geometry IndexedFaceSet
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appearance Appearance{material USE IC-BODY-EPOXY-04 }
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Shape { geometry IndexedFaceSet
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appearance Appearance{material USE IC-BODY-EPOXY-04 }
}
Shape { geometry IndexedFaceSet
{ creaseAngle 0.50 coordIndex [0,1,2,-1,3,1,0,-1]
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appearance Appearance{material USE IC-BODY-EPOXY-04 }
}
Shape { geometry IndexedFaceSet
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}}
appearance Appearance{material USE IC-BODY-EPOXY-04 }
}
Shape { geometry IndexedFaceSet
{ creaseAngle 0.50 coordIndex [0,1,2,-1,2,1,3,-1]
coord Coordinate { point [-0.315 0.472 0.354,-0.315 0.533 0.354,-0.315 0.472 0.295,-0.315 0.533 0.295]
}}
appearance Appearance{material USE IC-BODY-EPOXY-04 }
}
Shape { geometry IndexedFaceSet
{ creaseAngle 0.50 coordIndex [0,1,2,-1,3,1,0,-1]
coord Coordinate { point [-0.315 -0.276 0.295,-0.335 -0.472 0.295,-0.335 -0.276 0.295,-0.315 -0.472 0.295]
}}
appearance Appearance{material USE PIN-01 }
}
Shape { geometry IndexedFaceSet
{ creaseAngle 0.50 coordIndex [0,1,2,-1,3,1,0,-1]
coord Coordinate { point [-0.315 0.472 0.295,-0.335 0.276 0.295,-0.335 0.472 0.295,-0.315 0.276 0.295]
}}
appearance Appearance{material USE PIN-01 }
}
Shape { geometry IndexedFaceSet
{ creaseAngle 0.50 coordIndex [0,1,2,-1,2,1,3,-1]
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}}
appearance Appearance{material USE IC-BODY-EPOXY-04 }
}
Shape { geometry IndexedFaceSet
{ creaseAngle 0.50 coordIndex [0,1,2,-1,2,1,3,-1]
coord Coordinate { point [-0.315 0.098 0.354,-0.315 0.276 0.354,-0.315 0.098 0.295,-0.315 0.276 0.295]
}}
appearance Appearance{material USE IC-BODY-EPOXY-04 }
}
Shape { geometry IndexedFaceSet
{ creaseAngle 0.50 coordIndex [0,1,2,-1,3,1,0,-1]
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appearance Appearance{material USE PIN-01 }
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appearance Appearance{material USE PIN-01 }
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appearance Appearance{material USE PIN-01 }
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appearance Appearance{material USE PIN-01 }
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appearance Appearance{material USE PIN-01 }
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appearance Appearance{material USE PIN-01 }
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appearance Appearance{material USE PIN-01 }
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appearance Appearance{material USE PIN-01 }
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appearance Appearance{material USE PIN-01 }
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appearance Appearance{material USE PIN-01 }
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appearance Appearance{material USE PIN-01 }
}

View File

@@ -0,0 +1,27 @@
(module Thin-DFN4 (layer F.Cu) (tedit 5A13CB11)
(attr smd)
(fp_text reference U5 (at 0 -0.3) (layer F.Fab)
(effects (font (size 0.127 0.127) (thickness 0.03175)))
)
(fp_text value MIC5504-2.5YM5-TR (at 0 0.7) (layer F.Fab)
(effects (font (size 0.127 0.127) (thickness 0.03175)))
)
(fp_circle (center -0.3 0.3) (end -0.2 0.3) (layer F.Fab) (width 0.05))
(fp_line (start -0.5 -0.5) (end -0.5 0.5) (layer F.Fab) (width 0.05))
(fp_line (start 0.5 -0.5) (end -0.5 -0.5) (layer F.Fab) (width 0.05))
(fp_line (start 0.5 0.5) (end 0.5 -0.5) (layer F.Fab) (width 0.05))
(fp_line (start -0.5 0.5) (end 0.5 0.5) (layer F.Fab) (width 0.05))
(pad 2 smd trapezoid (at 0 0 45) (size 0.48 0.48) (layers F.Cu F.Paste F.Mask))
(pad 2 smd trapezoid (at 0.325 0.54) (size 0.25 0.22) (layers F.Cu F.Paste F.Mask))
(pad 1 smd trapezoid (at -0.325 0.54) (size 0.25 0.22) (layers F.Cu F.Paste F.Mask))
(pad 3 smd trapezoid (at 0.325 -0.54) (size 0.25 0.22) (layers F.Cu F.Paste F.Mask))
(pad 4 smd trapezoid (at -0.325 -0.54) (size 0.25 0.22) (layers F.Cu F.Paste F.Mask))
(pad 3 smd trapezoid (at 0.325 -0.43 180) (size 0.25 0.22) (rect_delta 0.2199 0 ) (layers F.Cu F.Paste F.Mask)
(solder_mask_margin 0.025))
(pad 4 smd trapezoid (at -0.325 -0.43) (size 0.25 0.22) (rect_delta 0.2199 0 ) (layers F.Cu F.Paste F.Mask)
(solder_mask_margin 0.025))
(pad 2 smd trapezoid (at 0.325 0.43 180) (size 0.25 0.22) (rect_delta 0.2199 0 ) (layers F.Cu F.Paste F.Mask)
(solder_mask_margin 0.025))
(pad 1 smd trapezoid (at -0.325 0.43) (size 0.25 0.22) (rect_delta 0.2199 0 ) (layers F.Cu F.Paste F.Mask)
(solder_mask_margin 0.025))
)

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62
bootloader_alt/Makefile Normal file
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@@ -0,0 +1,62 @@
# Makefile borrowed from https://github.com/cliffordwolf/icestorm/blob/master/examples/icestick/Makefile
#
# The following license is from the icestorm project and specifically applies to this file only:
#
# Permission to use, copy, modify, and/or distribute this software for any
# purpose with or without fee is hereby granted, provided that the above
# copyright notice and this permission notice appear in all copies.
#
# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
PROJ = TinyFPGA_B
PIN_DEF = pins.pcf
DEVICE = lp8k
all: $(PROJ).rpt $(PROJ).bin
%.blif: %.v
yosys -p 'synth_ice40 -top $(PROJ) -blif $@' $<
%.asc: $(PIN_DEF) %.blif
arachne-pnr -d 8k -P cm81 -o $@ -p $^
%.bin: %.asc
icepack $< $@
%.rpt: %.asc
icetime -d $(DEVICE) -mtr $@ $<
%_tb: %_tb.v %.v
iverilog -o $@ $^
%_tb.vcd: %_tb
vvp -N $< +vcd=$@
%_syn.v: %.blif
yosys -p 'read_blif -wideports $^; write_verilog $@'
%_syntb: %_tb.v %_syn.v
iverilog -o $@ $^ `yosys-config --datdir/ice40/cells_sim.v`
%_syntb.vcd: %_syntb
vvp -N $< +vcd=$@
prog: $(PROJ).bin
iceprog $<
sudo-prog: $(PROJ).bin
@echo 'Executing prog as root!!!'
sudo iceprog $<
clean:
rm -f $(PROJ).blif $(PROJ).asc $(PROJ).rpt $(PROJ).bin
.SECONDARY:
.PHONY: all prog clean

19588
bootloader_alt/TinyFPGA_B.asc Normal file
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@@ -0,0 +1,14 @@
# Generated by Yosys 0.7+336 (git sha1 adf1754, clang 3.8.0-2ubuntu4 -fPIC -Os)
.model TinyFPGA_B
.inputs
.outputs pin_pu pin_led
.names $false
.names $true
1
.names $undef
.names $false pin_led
1 1
.names $false pin_pu
1 1
.end

View File

@@ -0,0 +1,7 @@
module TinyFPGA_B (
output pin_pu,
output pin_led
);
assign pin_pu = 1'b0;
assign pin_led = 1'b0;
endmodule

View File

@@ -0,0 +1,88 @@
[Project]
ProjectVersion=2.0
Version=Lattice Semiconductor Corporation iCEcube - Release: 2017.01.27914 - Build Date: Jan 12 2017 19:10:45
ProjectName=bootloader_alt
Vendor=SiliconBlue
Synthesis=synplify
ProjectVFiles=../TinyFPGA_B.v
ProjectCFiles=
CurImplementation=bootloader_alt_Implmnt
Implementations=bootloader_alt_Implmnt
StartFromSynthesis=yes
IPGeneration=false
[bootloader_alt_Implmnt]
DeviceFamily=iCE40
Device=LP8K
DevicePackage=CM81
DevicePower=
NetlistFile=bootloader_alt_Implmnt/bootloader_alt.edf
AdditionalEDIFFile=
IPEDIFFile=
DesignLib=bootloader_alt_Implmnt/sbt/netlist/oadb-TinyFPGA_B
DesignView=_rt
DesignCell=TinyFPGA_B
SynthesisSDCFile=bootloader_alt_Implmnt/bootloader_alt.scf
UserPinConstraintFile=
UserSDCFile=
PhysicalConstraintFile=../pins.pcf
BackendImplPathName=
Devicevoltage=1.2
DevicevoltagePerformance=+/-5%(datasheet default)
DeviceTemperature=25
TimingAnalysisBasedOn=Typical
OperationRange=Commercial
TypicalCustomTemperature=25
WorstCustomTemperature=85
BestCustomTemperature=0
IOBankVoltages=topBank,3.3 bottomBank,3.3 leftBank,3.3 rightBank,3.3
derValue=0.85
TimingPathNumberStick=0
[lse options]
CarryChain=True
CarryChainLength=0
CommandLineOptions=
EBRUtilization=100.00
FSMEncodingStyle=Auto
FixGatedClocks=True
I/OInsertion=True
IntermediateFileDump=False
LoopLimit=1950
MaximalFanout=10000
MemoryInitialValueFileSearchPath=
NumberOfCriticalPaths=3
OptimizationGoal=Area
PropagateConstants=True
RAMStyle=Auto
ROMStyle=Auto
RWCheckOnRam=False
RemoveDuplicateRegisters=True
ResolvedMixedDrivers=False
ResourceSharing=True
TargetFrequency=
TopLevelUnit=
UseIORegister=Auto
VHDL2008=False
VerilogIncludeSearchPath=
[tool options]
PlacerEffortLevel=std
PlacerAutoLutCascade=yes
PlacerAutoRamCascade=yes
PlacerPowerDriven=no
PlacerAreaDriven=no
RouteWithTimingDriven=yes
RouteWithPinPermutation=yes
BitmapSPIFlashMode=yes
BitmapRAM4KInit=yes
BitmapInitRamBank=1111
BitmapOscillatorFR=low
BitmapEnableWarmBoot=yes
BitmapDisableHeader=no
BitmapSetSecurity=no
BitmapSetNoUsedIONoPullup=no
FloorPlannerShowFanInNets=yes
FloorPlannerShowFanOutNets=yes
HookTo3rdPartyTextEditor=

View File

@@ -0,0 +1,56 @@
#-- Synopsys, Inc.
#-- Project file C:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-B-Series\bootloader_alt\bootloader_alt\bootloader_alt_syn.prj
#project files
add_file -verilog -lib work "../TinyFPGA_B.v"
#implementation: "bootloader_alt_Implmnt"
impl -add bootloader_alt_Implmnt -type fpga
#implementation attributes
set_option -vlog_std v2001
set_option -project_relative_includes 1
#device options
set_option -technology SBTiCE40
set_option -part iCE40LP8K
set_option -package CM81
set_option -speed_grade
set_option -part_companion ""
#compilation/mapping options
# mapper_options
set_option -frequency auto
set_option -write_verilog 0
set_option -write_vhdl 0
# Silicon Blue iCE40
set_option -maxfan 10000
set_option -disable_io_insertion 0
set_option -pipe 1
set_option -retiming 0
set_option -update_models_cp 0
set_option -fixgatedclocks 2
set_option -fixgeneratedclocks 0
# NFilter
set_option -popfeed 0
set_option -constprop 0
set_option -createhierarchy 0
# sequential_optimization_options
set_option -symbolic_fsm_compiler 1
# Compiler Options
set_option -compiler_compatible 0
set_option -resource_sharing 1
#automatic place and route (vendor) options
set_option -write_apr_constraint 1
#set result format/file last
project -result_format "edif"
project -result_file ./bootloader_alt_Implmnt/bootloader_alt.edf
project -log_file "./bootloader_alt_Implmnt/bootloader_alt.srr"
impl -active "bootloader_alt_Implmnt"
project -run synthesis -clean

48
bootloader_alt/pins.pcf Normal file
View File

@@ -0,0 +1,48 @@
###############################################################################
# Family & Device: iCE40LP8K
# Package: CM81
###############################################################################
#set_io pin_1 A2
#set_io pin_2 A1
#set_io pin_3 B1
#set_io pin_4 C2
#set_io pin_5 C1
#set_io pin_6 D2
#set_io pin_7 D1
#set_io pin_8 E2
#set_io pin_9 E1
#set_io pin_10 G2
#set_io pin_11 H1
#set_io pin_12 J1
#set_io pin_13 H2
#set_io pin_14 H9
#set_io pin_15 D9
#set_io pin_16 D8
#set_io pin_17 C9
#set_io pin_18 A9
#set_io pin_19 B8
#set_io pin_20 A8
#set_io pin_21 B7
#set_io pin_22 A7
#set_io pin_23 B6
#set_io pin_24 A6
#set_io pin_25 G1
#set_io pin_26 J3
#set_io pin_27 J4
#set_io pin_28 H4
#set_io pin_29_miso H7
#set_io pin_30_cs F7
#set_io pin_31_mosi G6
#set_io pin_32_sck G7
#set_io pin_33 J8
#set_io pin_34 G9
#set_io pin_35 J9
#set_io pin_36 E8
#set_io pin_37 J2
set_io pin_led B3
#set_io pin_usbp B4
#set_io pin_usbn A4
set_io pin_pu A3
#set_io pin_clk B2

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dft/Makefile Normal file
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# Makefile borrowed from https://github.com/cliffordwolf/icestorm/blob/master/examples/icestick/Makefile
#
# The following license is from the icestorm project and specifically applies to this file only:
#
# Permission to use, copy, modify, and/or distribute this software for any
# purpose with or without fee is hereby granted, provided that the above
# copyright notice and this permission notice appear in all copies.
#
# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
PROJ = TinyFPGA_B
PIN_DEF = pins.pcf
DEVICE = lp8k
all: $(PROJ).rpt $(PROJ).bin
%.blif: %.v
yosys -p 'synth_ice40 -top $(PROJ) -blif $@' $<
%.asc: $(PIN_DEF) %.blif
arachne-pnr -d 8k -P cm81 -o $@ -p $^
%.bin: %.asc
icepack $< $@
%.rpt: %.asc
icetime -d $(DEVICE) -mtr $@ $<
%_tb: %_tb.v %.v
iverilog -o $@ $^
%_tb.vcd: %_tb
vvp -N $< +vcd=$@
%_syn.v: %.blif
yosys -p 'read_blif -wideports $^; write_verilog $@'
%_syntb: %_tb.v %_syn.v
iverilog -o $@ $^ `yosys-config --datdir/ice40/cells_sim.v`
%_syntb.vcd: %_syntb
vvp -N $< +vcd=$@
prog: $(PROJ).bin
iceprog $<
sudo-prog: $(PROJ).bin
@echo 'Executing prog as root!!!'
sudo iceprog $<
clean:
rm -f $(PROJ).blif $(PROJ).asc $(PROJ).rpt $(PROJ).bin
.SECONDARY:
.PHONY: all prog clean

121
dft/TinyFPGA_B.v Normal file
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module TinyFPGA_B (
input pin_clk,
input pin_usbp,
input pin_usbn,
input pin_pu,
input pin_led,
output pin_1,
output pin_2,
output pin_3,
output pin_4,
output pin_5,
output pin_6,
output pin_7,
output pin_8,
output pin_9,
output pin_10,
output pin_11,
output pin_12,
input pin_13,
output pin_14,
output pin_15,
output pin_16,
output pin_17,
output pin_18,
output pin_19,
output pin_20,
input pin_21,
input pin_22,
input pin_23,
input pin_24,
input pin_25,
input pin_26,
input pin_27,
input pin_28,
input pin_29_miso,
output pin_30_cs,
input pin_31_mosi,
output pin_32_sck,
input pin_33,
input pin_34,
input pin_35,
input pin_36,
input pin_37
);
// there are some decoupling caps just for the PLL on the board,
// let's pipe the clock through the PLL so we can test both the
// clock and PLL at once
wire clk_48mhz;
reg [19:0] clock_divider;
reg slow_clock;
SB_PLL40_CORE pll_inst (
.REFERENCECLK(pin_clk),
.PLLOUTCORE(clk_48mhz),
.PLLOUTGLOBAL(),
.EXTFEEDBACK(),
.DYNAMICDELAY(),
.RESETB(1'b1),
.BYPASS(1'b0),
.LATCHINPUTVALUE(),
.LOCK(),
.SDI(),
.SDO(),
.SCLK()
);
// Fin=16, Fout=48
defparam pll_inst.DIVR = 4'b0000;
defparam pll_inst.DIVF = 7'b0101111;
defparam pll_inst.DIVQ = 3'b100;
defparam pll_inst.FILTER_RANGE = 3'b001;
defparam pll_inst.FEEDBACK_PATH = "SIMPLE";
defparam pll_inst.DELAY_ADJUSTMENT_MODE_FEEDBACK = "FIXED";
defparam pll_inst.FDA_FEEDBACK = 4'b0000;
defparam pll_inst.DELAY_ADJUSTMENT_MODE_RELATIVE = "FIXED";
defparam pll_inst.FDA_RELATIVE = 4'b0000;
defparam pll_inst.SHIFTREG_DIV_MODE = 2'b00;
defparam pll_inst.PLLOUT_SELECT = "GENCLK";
defparam pll_inst.ENABLE_ICEGATE = 1'b0;
// divide the clock down to ensure two things:
// 1. clock is connected to FPGA
// 2. output clock is measurable by test-jig
assign pin_32_sck = slow_clock;
always @(posedge clk_48mhz) begin
if (clock_divider < 1000000) begin
clock_divider <= clock_divider + 1;
end else begin
slow_clock <= ~slow_clock;
clock_divider <= 0;
end
end
// pulling an input pin low will drive the corresponding
// output pin low as well. this is a simple way for the
// test jig to test all the IOs for opens and shorts
assign pin_1 = pin_21;// ? 1'bz : 0;
assign pin_2 = pin_22;// ? 1'bz : 0;
assign pin_3 = pin_23;// ? 1'bz : 0;
assign pin_4 = pin_24;// ? 1'bz : 0;
assign pin_5 = pin_25;// ? 1'bz : 0;
assign pin_6 = pin_26;// ? 1'bz : 0;
assign pin_7 = pin_27;// ? 1'bz : 0;
assign pin_8 = pin_28;// ? 1'bz : 0;
assign pin_9 = pin_29_miso;// ? 1'bz : 0;
assign pin_10 = pin_13;// ? 1'bz : 0;
assign pin_11 = pin_31_mosi;// ? 1'bz : 0;
assign pin_12 = pin_pu;// ? 1'bz : 0;
assign pin_30_cs = pin_33;// ? 1'bz : 0;
assign pin_14 = pin_34;// ? 1'bz : 0;
assign pin_15 = pin_35;// ? 1'bz : 0;
assign pin_16 = pin_36;// ? 1'bz : 0;
assign pin_17 = pin_37;// ? 1'bz : 0;
assign pin_18 = pin_led;// ? 1'bz : 0;
assign pin_19 = pin_usbp;// ? 1'bz : 0;
assign pin_20 = pin_usbn;// ? 1'bz : 0;
endmodule

48
dft/pins.pcf Normal file
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###############################################################################
# Family & Device: iCE40LP8K
# Package: CM81
###############################################################################
set_io pin_1 A2
set_io pin_2 A1
set_io pin_3 B1
set_io pin_4 C2
set_io pin_5 C1
set_io pin_6 D2
set_io pin_7 D1
set_io pin_8 E2
set_io pin_9 E1
set_io pin_10 G2
set_io pin_11 H1
set_io pin_12 J1
set_io pin_13 H2
set_io pin_14 H9
set_io pin_15 D9
set_io pin_16 D8
set_io pin_17 C9
set_io pin_18 A9
set_io pin_19 B8
set_io pin_20 A8
set_io pin_21 B7
set_io pin_22 A7
set_io pin_23 B6
set_io pin_24 A6
set_io pin_25 G1
set_io pin_26 J3
set_io pin_27 J4
set_io pin_28 H4
set_io pin_29_miso H7
set_io pin_30_cs F7
set_io pin_31_mosi H5
set_io pin_32_sck G7
set_io pin_33 J8
set_io pin_34 G9
set_io pin_35 J9
set_io pin_36 E8
set_io pin_37 J2
set_io pin_led B3
set_io pin_usbp B4
set_io pin_usbn A4
set_io pin_pu A3
set_io pin_clk B2

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# ##############################################################################
# iCEcube SDC
# Version: 2017.01.27914
# File Generated: Jul 9 2017 15:15:35
# ##############################################################################
####---- CreateClock list ----1
create_clock -period 62.50 -name {pin3_clk_16mhz} [get_ports {pin3_clk_16mhz}]

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# ##############################################################################
# iCEcube PCF
# Version: 2017.01.27914
# File Generated: Jun 24 2017 13:04:57
# Family & Device: iCE40LP8K
# Package: CM81
# ##############################################################################
###IOSet List 24
set_io pin13 J1
set_io pin15_sdi H7
set_io pin1_usb_dp A3
set_io pin20 E8
set_io pin2_usb_dn A4
set_io pin4 B2
set_io pin10 E1
set_io pin18 D9
set_io pin7 B1
set_io pin11 G1
set_io pin19 C9
set_io pin22 A8
set_io pin6 A1
set_io pin12 H1
set_io pin16_sck G7
set_io pin21 A9
set_io pin5 A2
set_io pin9 D1
set_io pin14_sdo G6
set_io pin24 A6
set_io pin8 C1
set_io pin17_ss F7
set_io pin23 A7
set_io pin3_clk_16mhz B4

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#-- Lattice, Inc.
#-- Project file C:\lscc\iCEcube2.2017.01\sbt_backend\Projects\template\template_lse.prj
#device
-a SBTiCE40
-d iCE40LP8K
-t CM81
#constraint file
-sdc "constraints/clk.sdc"
#options
-optimization_goal Area
-twr_paths 3
-bram_utilization 100.00
-ramstyle Auto
-romstyle Auto
-use_carry_chain 1
-carry_chain_length 0
-resource_sharing 1
-propagate_constants 1
-remove_duplicate_regs 1
-max_fanout 10000
-fsm_encoding_style Auto
-use_io_insertion 1
-use_io_reg auto
-resolve_mixed_drivers 0
-RWCheckOnRam 0
-fix_gated_clocks 1
-loop_limit 1950
-ver "verilog/TinyFPGA_B.v"
-p "C:/lscc/iCEcube2.2017.01/sbt_backend/Projects/template"
#set result format/file last
-output_edif template_Implmnt/template.edf
#set log file
-logfile "template_Implmnt/template_lse.log"

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@@ -0,0 +1,88 @@
[Project]
ProjectVersion=2.0
Version=Lattice Semiconductor Corporation iCEcube - Release: 2017.01.27914 - Build Date: Jan 12 2017 19:10:45
ProjectName=template
Vendor=SiliconBlue
Synthesis=synplify
ProjectVFiles=verilog/TinyFPGA_B.v=work
ProjectCFiles=
CurImplementation=template_Implmnt
Implementations=template_Implmnt
StartFromSynthesis=yes
IPGeneration=false
[lse options]
CarryChain=True
CarryChainLength=0
CommandLineOptions=
EBRUtilization=100.00
FSMEncodingStyle=Auto
FixGatedClocks=True
I/OInsertion=True
IntermediateFileDump=False
LoopLimit=1950
MaximalFanout=10000
MemoryInitialValueFileSearchPath=
NumberOfCriticalPaths=3
OptimizationGoal=Area
PropagateConstants=True
RAMStyle=Auto
ROMStyle=Auto
RWCheckOnRam=False
RemoveDuplicateRegisters=True
ResolvedMixedDrivers=False
ResourceSharing=True
TargetFrequency=
TopLevelUnit=
UseIORegister=Auto
VHDL2008=False
VerilogIncludeSearchPath=
[template_Implmnt]
DeviceFamily=iCE40
Device=LP8K
DevicePackage=CM81
DevicePower=
NetlistFile=template_Implmnt/template.edf
AdditionalEDIFFile=
IPEDIFFile=
DesignLib=template_Implmnt/sbt/netlist/oadb-TinyFPGA_B
DesignView=_rt
DesignCell=TinyFPGA_B
SynthesisSDCFile=template_Implmnt/template.scf
UserPinConstraintFile=
UserSDCFile=constraints/clk.sdc
PhysicalConstraintFile=constraints/pins.pcf
BackendImplPathName=
Devicevoltage=1.14
DevicevoltagePerformance=+/-5%(datasheet default)
DeviceTemperature=85
TimingAnalysisBasedOn=Worst
OperationRange=Commercial
TypicalCustomTemperature=25
WorstCustomTemperature=85
BestCustomTemperature=0
IOBankVoltages=topBank,3.3 bottomBank,3.3 leftBank,3.3 rightBank,3.3
derValue=1.03369
TimingPathNumberStick=0
[tool options]
PlacerEffortLevel=std
PlacerAutoLutCascade=yes
PlacerAutoRamCascade=yes
PlacerPowerDriven=no
PlacerAreaDriven=no
RouteWithTimingDriven=yes
RouteWithPinPermutation=yes
BitmapSPIFlashMode=yes
BitmapRAM4KInit=yes
BitmapInitRamBank=1111
BitmapOscillatorFR=low
BitmapEnableWarmBoot=yes
BitmapDisableHeader=no
BitmapSetSecurity=no
BitmapSetNoUsedIONoPullup=no
FloorPlannerShowFanInNets=yes
FloorPlannerShowFanOutNets=yes
HookTo3rdPartyTextEditor=no

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#-- Synopsys, Inc.
#-- Version L-2016.09L+ice40
#-- Project file C:\lscc\iCEcube2.2017.01\sbt_backend\Projects\template\template_syn.prd
#-- Written on Thu Jun 29 00:07:23 2017
#
### Watch Implementation type ###
#
watch_impl -all
#
### Watch Implementation properties ###
#
watch_prop -clear

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#-- Synopsys, Inc.
#-- Version L-2016.09L+ice40
#-- Project file C:\lscc\iCEcube2.2017.01\sbt_backend\Projects\template\template_syn.prj
#-- Written on Sun Jun 04 23:11:47 2017
#project files
add_file -verilog -lib work "verilog/TinyFPGA_B.v"
#implementation: "template_Implmnt"
impl -add template_Implmnt -type fpga
#
#implementation attributes
set_option -vlog_std v2001
set_option -project_relative_includes 1
#device options
set_option -technology SBTiCE40
set_option -part iCE40LP8K
set_option -package CM81
set_option -speed_grade
set_option -part_companion ""
#compilation/mapping options
# hdl_compiler_options
set_option -distributed_compile 0
# mapper_without_write_options
set_option -frequency auto
set_option -srs_instrumentation 1
# mapper_options
set_option -write_verilog 0
set_option -write_vhdl 0
# Lattice iCE40
set_option -maxfan 10000
set_option -rw_check_on_ram 0
set_option -disable_io_insertion 0
set_option -pipe 1
set_option -retiming 0
set_option -update_models_cp 0
set_option -fix_gated_and_generated_clocks 1
set_option -run_prop_extract 1
# NFilter
set_option -no_sequential_opt 0
# sequential_optimization_options
set_option -symbolic_fsm_compiler 1
# Compiler Options
set_option -compiler_compatible 0
set_option -resource_sharing 1
# Compiler Options
set_option -auto_infer_blackbox 0
#automatic place and route (vendor) options
set_option -write_apr_constraint 1
#set result format/file last
project -result_file "template_Implmnt/template.edf"
impl -active template_Implmnt
project -run synthesis -clean

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module TinyFPGA_B (
inout pin1_usb_dp,
inout pin2_usb_dn,
input pin3_clk_16mhz,
inout pin4,
inout pin5,
inout pin6,
inout pin7,
inout pin8,
inout pin9,
inout pin10,
inout pin11,
inout pin12,
inout pin13,
inout pin14_sdo,
inout pin15_sdi,
inout pin16_sck,
inout pin17_ss,
inout pin18,
inout pin19,
inout pin20,
inout pin21,
inout pin22,
inout pin23,
inout pin24
);
// left side of board
assign pin1_usb_dp = 1'bz;
assign pin2_usb_dn = 1'bz;
assign pin4 = 1'bz;
assign pin5 = 1'bz;
assign pin6 = 1'bz;
assign pin7 = 1'bz;
assign pin8 = 1'bz;
assign pin9 = 1'bz;
assign pin10 = 1'bz;
assign pin11 = 1'bz;
assign pin12 = 1'bz;
assign pin13 = 1'bz;
// right side of board
assign pin14_sdo = 1'bz;
assign pin15_sdi = 1'bz;
assign pin16_sck = 1'bz;
assign pin17_ss = 1'bz;
assign pin18 = 1'bz;
assign pin19 = 1'bz;
assign pin20 = 1'bz;
assign pin21 = 1'bz;
assign pin22 = 1'bz;
assign pin23 = 1'bz;
assign pin24 = 1'bz;
endmodule

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# Makefile borrowed from https://github.com/cliffordwolf/icestorm/blob/master/examples/icestick/Makefile
#
# The following license is from the icestorm project and specifically applies to this file only:
#
# Permission to use, copy, modify, and/or distribute this software for any
# purpose with or without fee is hereby granted, provided that the above
# copyright notice and this permission notice appear in all copies.
#
# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
PROJ = TinyFPGA_B
PIN_DEF = pins.pcf
DEVICE = lp8k
all: $(PROJ).rpt $(PROJ).bin
%.blif: %.v
yosys -p 'synth_ice40 -top $(PROJ) -blif $@' $<
%.asc: $(PIN_DEF) %.blif
arachne-pnr -d 8k -P cm81 -o $@ -p $^
%.bin: %.asc
icepack $< $@
%.rpt: %.asc
icetime -d $(DEVICE) -mtr $@ $<
%_tb: %_tb.v %.v
iverilog -o $@ $^
%_tb.vcd: %_tb
vvp -N $< +vcd=$@
%_syn.v: %.blif
yosys -p 'read_blif -wideports $^; write_verilog $@'
%_syntb: %_tb.v %_syn.v
iverilog -o $@ $^ `yosys-config --datdir/ice40/cells_sim.v`
%_syntb.vcd: %_syntb
vvp -N $< +vcd=$@
prog: $(PROJ).bin
iceprog $<
sudo-prog: $(PROJ).bin
@echo 'Executing prog as root!!!'
sudo iceprog $<
clean:
rm -f $(PROJ).blif $(PROJ).asc $(PROJ).rpt $(PROJ).bin
.SECONDARY:
.PHONY: all prog clean

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Install [icestorm](http://www.clifford.at/icestorm/) for your computer once:
```sh
sudo apt-get install build-essential clang bison flex libreadline-dev \
gawk tcl-dev libffi-dev git mercurial graphviz \
xdot pkg-config python python3 libftdi-dev
mkdir icestorm-build
cd icestorm-build
git clone https://github.com/cliffordwolf/icestorm.git icestorm
cd icestorm
make -j$(nproc)
sudo make install
cd ..
git clone https://github.com/cseed/arachne-pnr.git arachne-pnr
cd arachne-pnr
make -j$(nproc)
sudo make install
cd ..
git clone https://github.com/cliffordwolf/yosys.git yosys
cd yosys
make -j$(nproc)
sudo make install
cd ..
```
Copy the icestorm_template directory to a new project directory with a name of your choosing:
```shell
cp icestorm_template ~/my_tinyfpga_project
```
Build the project:
```shell
cd ~/my_tinyfpga_project
make
```
The programmer script lives in this repo in [programmer/tinyfpgab.py](https://github.com/tinyfpga/TinyFPGA-B-Series/blob/master/programmer/tinyfpgab.py) Program the TinyFPGA B-series board with the bitstream:
```shell
python $TINYFPGA_B_REPO/programmer/tinyfpgab.py --program TinyFPGA_B.bin
```

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///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
///
/// Top-Level Verilog Module
///
/// Only include pins the design is actually using. Make sure that the pin is
/// given the correct direction: input vs. output vs. inout
///
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
module TinyFPGA_B (
output pin1_usb_dp,
output pin2_usb_dn,
input pin3_clk_16mhz,
//inout pin4,
//inout pin5,
//inout pin6,
//inout pin7,
//inout pin8,
//inout pin9,
//inout pin10,
//inout pin11,
//inout pin12,
output pin13,
//inout pin14_sdo,
//inout pin15_sdi,
//inout pin16_sck,
//inout pin17_ss,
//inout pin18,
//inout pin19,
//inout pin20,
//inout pin21,
//inout pin22,
//inout pin23,
//inout pin24
);
reg [23:0] counter;
always @(posedge pin3_clk_16mhz) counter <= counter + 1;
/// left side of board
assign pin1_usb_dp = 1'b0;
assign pin2_usb_dn = 1'b0;
//assign pin4 = 1'bz;
//assign pin5 = 1'bz;
//assign pin6 = 1'bz;
//assign pin7 = 1'bz;
//assign pin8 = 1'bz;
//assign pin9 = 1'bz;
//assign pin10 = 1'bz;
//assign pin11 = 1'bz;
//assign pin12 = 1'bz;
assign pin13 = counter[23];
/// right side of board
//assign pin14_sdo = 1'bz;
//assign pin15_sdi = 1'bz;
//assign pin16_sck = 1'bz;
//assign pin17_ss = 1'bz;
//assign pin18 = 1'bz;
//assign pin19 = 1'bz;
//assign pin20 = 1'bz;
//assign pin21 = 1'bz;
//assign pin22 = 1'bz;
//assign pin23 = 1'bz;
//assign pin24 = 1'bz;
endmodule

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### left side of board
set_io --warn-no-port pin1_usb_dp A3
set_io --warn-no-port pin2_usb_dn A4
set_io --warn-no-port pin3_clk_16mhz B4
set_io --warn-no-port pin4 B2
set_io --warn-no-port pin5 A2
set_io --warn-no-port pin6 A1
set_io --warn-no-port pin7 B1
set_io --warn-no-port pin8 C1
set_io --warn-no-port pin9 D1
set_io --warn-no-port pin10 E1
set_io --warn-no-port pin11 G1
set_io --warn-no-port pin12 H1
set_io --warn-no-port pin13 J1
### right side of board
set_io --warn-no-port pin14_sdo G6
set_io --warn-no-port pin15_sdi H7
set_io --warn-no-port pin16_sck G7
set_io --warn-no-port pin17_ss F7
set_io --warn-no-port pin18 D9
set_io --warn-no-port pin19 C9
set_io --warn-no-port pin20 E8
set_io --warn-no-port pin21 A9
set_io --warn-no-port pin22 A8
set_io --warn-no-port pin23 A7
set_io --warn-no-port pin24 A6