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https://github.com/tinyfpga/TinyFPGA-BX.git
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69 lines
1.6 KiB
Plaintext
69 lines
1.6 KiB
Plaintext
#-- Synopsys, Inc.
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#-- Version L-2016.09L+ice40
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#-- Project file C:\lscc\iCEcube2.2017.01\sbt_backend\Projects\template\template_syn.prj
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#-- Written on Sun Jun 04 23:11:47 2017
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#project files
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add_file -verilog -lib work "verilog/TinyFPGA_B.v"
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#implementation: "template_Implmnt"
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impl -add template_Implmnt -type fpga
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#
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#implementation attributes
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set_option -vlog_std v2001
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set_option -project_relative_includes 1
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#device options
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set_option -technology SBTiCE40
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set_option -part iCE40LP8K
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set_option -package CM81
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set_option -speed_grade
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set_option -part_companion ""
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#compilation/mapping options
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# hdl_compiler_options
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set_option -distributed_compile 0
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# mapper_without_write_options
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set_option -frequency auto
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set_option -srs_instrumentation 1
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# mapper_options
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set_option -write_verilog 0
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set_option -write_vhdl 0
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# Lattice iCE40
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set_option -maxfan 10000
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set_option -rw_check_on_ram 0
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set_option -disable_io_insertion 0
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set_option -pipe 1
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set_option -retiming 0
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set_option -update_models_cp 0
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set_option -fix_gated_and_generated_clocks 1
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set_option -run_prop_extract 1
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# NFilter
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set_option -no_sequential_opt 0
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# sequential_optimization_options
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set_option -symbolic_fsm_compiler 1
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# Compiler Options
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set_option -compiler_compatible 0
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set_option -resource_sharing 1
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# Compiler Options
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set_option -auto_infer_blackbox 0
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#automatic place and route (vendor) options
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set_option -write_apr_constraint 1
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#set result format/file last
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project -result_file "template_Implmnt/template.edf"
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impl -active template_Implmnt
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project -run synthesis -clean
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