mirror of
https://github.com/tinyfpga/TinyFPGA-BX.git
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68 lines
1.8 KiB
Verilog
68 lines
1.8 KiB
Verilog
///////////////////////////////////////////////////////////////////////////////
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///////////////////////////////////////////////////////////////////////////////
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///
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/// Top-Level Verilog Module
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///
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/// Only include pins the design is actually using. Make sure that the pin is
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/// given the correct direction: input vs. output vs. inout
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///
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///////////////////////////////////////////////////////////////////////////////
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///////////////////////////////////////////////////////////////////////////////
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module TinyFPGA_B (
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output pin1_usb_dp,
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output pin2_usb_dn,
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input pin3_clk_16mhz,
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//inout pin4,
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//inout pin5,
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//inout pin6,
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//inout pin7,
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//inout pin8,
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//inout pin9,
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//inout pin10,
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//inout pin11,
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//inout pin12,
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output pin13,
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//inout pin14_sdo,
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//inout pin15_sdi,
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//inout pin16_sck,
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//inout pin17_ss,
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//inout pin18,
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//inout pin19,
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//inout pin20,
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//inout pin21,
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//inout pin22,
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//inout pin23,
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//inout pin24
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);
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reg [23:0] counter;
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always @(posedge pin3_clk_16mhz) counter <= counter + 1;
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/// left side of board
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assign pin1_usb_dp = 1'b0;
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assign pin2_usb_dn = 1'b0;
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//assign pin4 = 1'bz;
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//assign pin5 = 1'bz;
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//assign pin6 = 1'bz;
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//assign pin7 = 1'bz;
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//assign pin8 = 1'bz;
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//assign pin9 = 1'bz;
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//assign pin10 = 1'bz;
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//assign pin11 = 1'bz;
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//assign pin12 = 1'bz;
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assign pin13 = counter[23];
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/// right side of board
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//assign pin14_sdo = 1'bz;
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//assign pin15_sdi = 1'bz;
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//assign pin16_sck = 1'bz;
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//assign pin17_ss = 1'bz;
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//assign pin18 = 1'bz;
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//assign pin19 = 1'bz;
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//assign pin20 = 1'bz;
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//assign pin21 = 1'bz;
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//assign pin22 = 1'bz;
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//assign pin23 = 1'bz;
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//assign pin24 = 1'bz;
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endmodule
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