salfter/corexy-pcb-mill
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Correcting homing failure bug. Removed compilation warning.

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This commit is contained in:
adichell
2019-01-12 19:53:04 +01:00
parent 4b73e24f73
commit a94c8fb14d
2 changed files with 3 additions and 2 deletions
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2
firmware/grbl_port/common_src/limits.c
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@@ -268,7 +268,7 @@ void SW_DEBOUNCE_TIMER_ISR()
{
WDTCSR &= ~(1<<WDIE); // Disable watchdog timer.
#endif
if (sys.state != STATE_ALARM) { // Ignore if already in alarm state.
if (sys.state != STATE_HOMING && sys.state != STATE_ALARM) { // Ignore if already in alarm state and during homing.
if (!(sys_rt_exec_alarm)) {
// Check limit pin state.
if (limits_get_state()) {

3
firmware/grbl_port/common_src/planner.c
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@@ -273,9 +273,10 @@ uint8_t plan_check_full_buffer()
// TODO: After this for-loop, we don't touch the stepper algorithm data. Might be a good idea
// to try to keep these types of things completely separate from the planner for portability.
int32_t target_steps[N_AXIS];
float unit_vec[N_AXIS], delta_mm,delta_mm_signed;
float unit_vec[N_AXIS], delta_mm;
uint8_t idx;
#ifdef COREXY
float delta_mm_signed;
float corexy_dir_invert_X, corexy_dir_invert_Y, corexy_dir_invert_Z;
corexy_dir_invert_X = bit_istrue(settings.dir_invert_mask,bit(X_AXIS)) ? -1 : 1;