Synchronise input pins and set LVTTL levels. More correct, but doesn't help the

read issues.

FluxEngine.cydsn/FluxEngine.cydwr

@@ -3687,6 +3687,9 @@
       <Group key="2">
         <Data key="Port Format" value="2,4" />
       </Group>
+      <Group key="3">
+        <Data key="Port Format" value="2,0" />
+      </Group>
     </Group>
     <Group key="41e2d8ed-5494-4d8c-8ff7-f4f789cece51">
       <Group key="0">
@@ -3836,7 +3839,7 @@
     </Group>
     <Group key="fbd1f839-40f9-498e-a48b-5f3048ea5c3d/52f31aa9-2f0a-497d-9a1f-1424095e13e6">
       <Group key="0">
-        <Data key="Port Format" value="2,0" />
+        <Data key="Port Format" value="2,5" />
       </Group>
     </Group>
     <Group key="fede1767-f3fd-4021-b3d7-8f9d88f36f9b">

FluxEngine.cydsn/FluxEngine.cyprj

@@ -3667,6 +3667,6 @@
 </ignored_deps>
 </CyGuid_495451fe-d201-4d01-b22d-5d3f5609ac37>
 <boot_component v="" />
-<current_generation v="23" />
+<current_generation v="60" />
 </CyGuid_fec8f9e8-2365-4bdb-96d3-a4380222e01b>
 </CyXmlSerializer>