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50 Commits

Author SHA1 Message Date
David Given
669c19882a Update firmware image. 2022-08-07 14:22:43 +02:00
David Given
3c17e74f6d Bump the protocol version to ensure people upgrade. 2022-03-26 21:54:29 +00:00
David Given
22e65227fb Increase the generated pulse width to try and generate a stronger signal. This 
does seem to make Amiga disks read more reliably.
 2022-03-15 23:56:49 +00:00
David Given
d120790da7 Update firmware to version 16. 2021-12-31 20:24:51 +00:00
David Given
462bd9ae5e Rewrite the sampler pulse detection... again. 2021-12-12 23:13:23 +00:00
David Given
b8a3e8085e Fix after merge. 2021-12-12 19:58:19 +00:00
David Given
8d04931f9f Turns out the high density pin is asserted when _double_ density. Set it 
correctly.
 2021-12-10 20:07:02 +00:00
David Given
2584a25527 Update components and binary. 2021-12-10 19:55:06 +00:00
David Given
5f4f2f10d7 Update FluxEngine components and rebuild firmware. 2021-05-25 19:11:32 +01:00
David Given
27c2c9045e Update sequencer to not lose one tick from every non-zero interval. 2021-01-18 00:27:00 +01:00
David Given
c2c51bbe33 Fix after merge. 2021-01-09 00:02:14 +01:00
David Given
e53b7ecd8b Rebuild firmware. 2021-01-05 01:51:29 +01:00
David Given
884edfd497 Tweak the Mac encoder parameters to work. 2021-01-04 23:06:15 +01:00
David Given
83dd9e462e Fix sequencer bug where intervals of 0 would go horribly wrong. 2021-01-04 22:06:19 +01:00
David Given
d60900262b Remove the pulse converters from the sampler (the new sampler doesn't require 
them). Update firmware.
 2020-06-25 21:07:58 +02:00
David Given
2b53ac057c Fix some bugs which allow erasing tracks with F_FRAME_WRITE_CMD to work again. 
(F_FRAME_ERASE_CMD always worked.)
 2020-05-13 23:45:58 +02:00
David Given
a9e30c1e49 Fix an off-by-one error in the sequencer that should have it generating correct 
sequences.
 2020-04-03 22:58:51 +02:00
David Given
972c8c6b61 Fix off-by-one sampler error, so now the clock rates are right again. 2020-04-03 22:27:33 +02:00
David Given
64694580cd Remember to bump the protocol number after the bytecode change. 2020-04-03 21:46:51 +02:00
David Given
0644d6d965 Remove some stray tracing (which was causing problems). Fix a potential problem 
where sampleclock posedges could be lost in the sequencer.
 2020-03-29 23:11:53 +02:00
David Given
a075694d8e Rewrite the sequencer to work with the new six bit bytecode. Fiddle with the 
USB stuff a lot in an attempt to resolve the weird packet loss issue.
 2020-03-29 15:10:35 +02:00
David Given
1b48ea20c4 Remove the cruncher. 2020-03-20 00:06:07 +01:00
David Given
1025bd857b Don't crashloop if the USB's not connected, as it causes the drives to be 
constantly reprobed (which runs the motor).
 2020-02-27 22:32:27 +01:00
David Given
c47a563790 Don't seek to track -1 on homing (it appears to upset 8" drives). Detect which 
drives are present, so that if only a single drive is attached then it's always
track 0, regardless of which connector it's on.
 2020-02-24 21:47:40 +01:00
David Given
647862cdbd Update the firmware for the new cruncher. 2020-02-18 22:13:41 +01:00
David Given
2df9920209 Rename test bulktransport to test bandwidth; avoid watchdog failures while the 
bandwidth test is running.
 2020-02-18 19:12:52 +01:00
David Given
1a6c6b5420 The bandwidth tester now tests bandwidth in both directions. It looks like my 
default USB port only gets about 500kB/s write bandwidth. However, when plugged
into a port with 850kB/s, I still get underrun errors...
 2020-02-17 23:58:40 +01:00
David Given
edc56d44d6 Non-functioning archive checkin: You can only have 120-odd DMA buffers, so my 
last 'fix' was in fact non-functional.
 2020-02-17 23:28:40 +01:00
David Given
ef4eff0195 So writing now works, but only if USB DMA is enabled. But that breaks reading. 
I've worked round this in a simple but brute force manner and it now looks as
if reading *and* writing work, more or less. There does still seem to be the
odd bad sector when writing 1440kB disks.
 2020-02-17 21:41:01 +01:00
David Given
df8d45bf66 Rework the output fifo to be a bit more correct about the sync signals, which 
in turn allows the sequencer to lose less time --- this gets the effective
clock rate down to about 1.01us. However we still seem to lose the last sector
on 18-sector disks and there are some disk reads so something is still wrong.
 2020-02-17 00:13:13 +01:00
David Given
387a86969a Some verilog optimisations which shave off a few p-terms. 2020-02-15 12:15:51 +01:00
David Given
acb5059d17 Rewrite the sampler *again* to, hopefully, be more stable and not lose ticks. 
Luckily, we have just enough space in the FPGA to use an actual logic counter,
which simplifies things hugely.
 2020-02-15 12:09:19 +01:00
David Given
29bdfc043a Allow fractional revolutions and non-synced reading. Find more things which 
need fixing in the firmware sampler.
 2020-01-27 22:52:25 +01:00
David Given
933ffe7ab4 Find and attempt to fix a memory corruption error when sampling --- if the next 
fragment arrives from the sampler before usbbuffer has finished being
transmitted via USB, it'll get overwritten. I've disabled DMA USB to make the
code easier to understand and made sure that we flush things more rigorously.
This may help the weird pipe errors, too.
 2020-01-27 21:40:27 +01:00
David Given
b0c675c589 Improved error messages when using fe-rpm and it doesn't work. 2020-01-12 01:34:12 +01:00
David Given
d77841c3b7 Add the ability to fake the index pulse source, allowing old drives to be used 
with FluxEngine.
 2020-01-12 01:23:47 +01:00
David Given
bcc9e9d9a5 Bump the protocol number (I forgot last time I changed the protocol). 2020-01-10 21:04:33 +01:00
David Given
c187b79d80 Add a 300RPM clock on 3[0] and a 360RPM clock on 3[1], for use with faking 
index pulses to the drive.
 2019-12-12 20:34:44 +01:00
David Given
edbe624c5a Hopefully, finally, fix the hang-on-read issue. 2019-12-12 20:09:49 +01:00
David Given
44e2334815 Typo fix. Make sure that both drives get deselected when the motor stops (to 
make the LEDs go out).
 2019-12-12 00:17:59 +01:00
David Given
b448ab7917 Finally squeeze everything in to the Verilog sampler. It does seem to work 
better... the the USB hangup problem persists. Mac disks are still
nigh-unreadable.
 2019-12-12 00:12:20 +01:00
David Given
072a097003 Archival (non-functioning) checkin of Verilog-based sampler code. Sadly, we've 
run into size limits for the device, and I need to slim down.
 2019-12-11 22:51:27 +01:00
David Given
a66e704bab Start ripping out the awful UDB-based sampler code, replacing it with a Verilog 
one and a standalone FIFO. This gets the FIFO working.
 2019-12-11 21:13:57 +01:00
David Given
32bb956710 Detect voltage levels *correctly*. 2019-12-11 00:05:34 +01:00
David Given
f436d6b582 Add a feature where we can measure the FDD bus signal voltages using the PSoC's 
ADCs. Increase the track step pulse width to 6us, because.
 2019-12-10 22:36:18 +01:00
David Given
91d6e9aeb9 Rewrite the sequencer engine with a separate fifo component and a pure verilog 
sequencer --- much easier to understand. We can write disks again!
 2019-11-25 20:52:13 +01:00
David Given
a40b26ff46 Archival checkin for trying to figure out why writes no longer work. 2019-11-24 15:14:32 +01:00
David Given
ebcb9c4bb0 Switch the output lines to open-drain drive low. 2019-11-24 02:06:45 +01:00
David Given
c266779433 Fix a bug where index pulses where being turned into flux pulses on read, 
leading to completely broken data whenever an index pulse happened.
 2019-08-27 23:58:07 +02:00
David Given
55f3354287 Add precompiled hex for the firmware. 2019-08-15 21:52:11 +02:00