David Given
7d88673ed5
Merge from trunk.
2021-01-05 01:36:54 +01:00
David Given
7f5d96382b
Update PSoC components.
2021-01-04 20:16:15 +01:00
David Given
c78ed2c6ad
Add the TK43 pin, which goes low when seeking to track 43 or above.
2020-09-10 21:48:30 +02:00
David Given
64694580cd
Remember to bump the protocol number after the bytecode change.
2020-04-03 21:46:51 +02:00
David Given
df8d45bf66
Rework the output fifo to be a bit more correct about the sync signals, which
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in turn allows the sequencer to lose less time --- this gets the effective
clock rate down to about 1.01us. However we still seem to lose the last sector
on 18-sector disks and there are some disk reads so something is still wrong.
2020-02-17 00:13:13 +01:00
David Given
6389e8a756
Update pin number (which was wrong).
2019-12-12 20:35:20 +01:00
David Given
c187b79d80
Add a 300RPM clock on 3[0] and a 360RPM clock on 3[1], for use with faking
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index pulses to the drive.
2019-12-12 20:34:44 +01:00
David Given
91d6e9aeb9
Rewrite the sequencer engine with a separate fifo component and a pure verilog
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sequencer --- much easier to understand. We can write disks again!
2019-11-25 20:52:13 +01:00
David Given
a40b26ff46
Archival checkin for trying to figure out why writes no longer work.
2019-11-24 15:14:32 +01:00
David Given
7a775afaea
Make sure that CounterClock is actually 12MHz, and not 12-ish MHz. Doesn't
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help.
2019-07-10 20:26:17 +02:00
David Given
c27c4fe312
Synchronise input pins and set LVTTL levels. More correct, but doesn't help the
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read issues.
2019-07-10 19:48:03 +02:00
David Given
ad295c683c
The sampler pulse conversion now uses BUS_CLK as the sample clock.
2019-07-09 22:43:46 +02:00
David Given
98ea5e9600
Connect up pins 2.3, 2.4 and 2.5 for debugging with a logic analyser.
2019-07-08 01:08:05 +02:00
David Given
ce6077fa22
Apply Denis Kushch's timing fixes to the schematic. No more warnings on builds!
2019-07-08 00:52:59 +02:00
David Given
1d22111f4e
Update components.
2019-04-21 01:16:25 +02:00
David Given
da8cae61b7
Add a debug UART back on pin 2.0 to get some semblance of debug information off
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the board. Discover a fun edge case where output transfers that were an exact
number of frames weren't being terminated correctly.
2019-04-06 17:59:23 +02:00
David Given
039d6b5fdd
More fiddling with the UDB sampler. Still doesn't work.
2019-02-26 22:37:45 +01:00
David Given
34a4c888b5
Rewrite the Verilog *again*, and increase the CPU clock rate --- it's now a
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little more reliable at reading long intervals off disk, but does seem to be
doing it. I'm going to definitely need some better sampling logic here and
probably a FIFO. But it'll do for now.
2019-02-23 19:51:27 +01:00
David Given
9f64de0c49
Do a recalibrate when retrying a track read --- it makes things a bit more
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reliable.
2019-02-09 22:55:46 +01:00
David Given
59eae19af2
Apply component update.
2018-12-14 19:11:36 +01:00
David Given
8f1cef48b1
Realise that the weird data dropouts were due to a stray capacitor on the
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board... so remove it. Better now. Also realise that PSoC Creator lies to you
about clocks, so adjust the sample clock to be derivable from the USB clock,
making it both the right frequency and much more accurate --- decode success is
dramatically improved (presumably due to less jitter). Redesign the capture
logic to use a timer; simpler now.
2018-10-06 18:32:57 +02:00
David Given
339cdd5105
Add a partially working MFM decoder --- MFM's fine, it's aligning to sync bytes
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which is hard.
2018-10-04 00:02:13 +02:00
David Given
fccabb3266
Add back in the hacky output file, for testing; replace the capture logic with
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an upcounter, and replace the pulse-in-high-bit stuff.
2018-10-03 19:45:27 +02:00
David Given
913829afbb
Discover timers; drastically simplify and betterify everything.
2018-10-02 00:17:37 +02:00
David Given
51cb1ae785
We just read our first floppy! Turns out the secret is to, once again, remove
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C7 from the board as it's preventing the READ DATA line showing anything.
2018-10-01 23:30:51 +02:00
David Given
4e19882d76
Archival checkin of messed-about non-working code to actually read data from
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disk. Something's wrong with the DMA; requesting a transfer every 2us with a TD
size of 64 bytes is somehow leading to an nrq interrupt every 8us. Mysterious.
2018-09-30 01:13:39 +02:00
David Given
755ae2950d
Attempt to DMA data gibberish data from a fake acquisition unit and send it out
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over USB.
2018-09-23 02:05:20 +02:00
David Given
9d00a1e5ea
Bolt on USB UART.
2018-09-22 22:08:49 +02:00
David Given
a59c764dc5
Initial project boilerplate.
2018-09-22 21:44:33 +02:00
