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41 Commits

Author SHA1 Message Date
David Given
c21177e2aa Finally make things work in release mode! 2019-05-01 13:06:43 +02:00
David Given
da8cae61b7 Add a debug UART back on pin 2.0 to get some semblance of debug information off 
the board. Discover a fun edge case where output transfers that were an exact
number of frames weren't being terminated correctly.
 2019-04-06 17:59:23 +02:00
David Given
bcc5a5f2cd Interim but working support for crunched data streams when reading from the 
device; writes haven't been converted yet. Reduces the bandiwidth from about
800kB/s to about 500kB/s, which is about what I thought.
 2019-03-26 23:03:19 +01:00
David Given
1d6f112b53 Remove the old logic-based sequencer. 2019-02-28 21:29:01 +01:00
David Given
f20ad8368a Non-working basis of a UDB datapath based sequencer. No more clock errors. 2019-02-28 01:03:58 +01:00
David Given
08cb20fd1d Remove the old, broken, Verilog sampler. 2019-02-27 23:57:13 +01:00
David Given
6bcd9a6644 The UDB-based pulse generator is back. The problem was I was trying to write to 
a HD disk (also the logic was wrong). I think my new Sony drive doesn't
autoselect.
 2019-02-27 23:34:55 +01:00
David Given
b8138aef40 Replace the UDB based pulse generator with the old counter-based one, which 
seems to work.
 2019-02-27 23:18:19 +01:00
David Given
462d15369e Create a pulse generator UDB component --- hopefully cheaper than what we're currently doing. 2019-02-26 23:33:06 +01:00
David Given
039d6b5fdd More fiddling with the UDB sampler. Still doesn't work. 2019-02-26 22:37:45 +01:00
David Given
74c6c6db56 Non-working attempt at replacing the sampler with a UDB datapath (so I can use 
the FIFO).
 2019-02-24 14:50:33 +01:00
David Given
34a4c888b5 Rewrite the Verilog *again*, and increase the CPU clock rate --- it's now a 
little more reliable at reading long intervals off disk, but does seem to be
doing it. I'm going to definitely need some better sampling logic here and
probably a FIFO. But it'll do for now.
 2019-02-23 19:51:27 +01:00
David Given
753a4a21ef Rewrite the sampler Verilog to use much more consistent logic. Still doesn't 
work for long intervals, though.
 2019-02-23 12:42:42 +01:00
David Given
6a1327e3f6 Attempt to translate the sequencer into Verilog and have it handle long 
intervals properly.
 2019-02-23 00:50:36 +01:00
David Given
970668aca5 Non-working attempt to replace the playback logic with Verilog. 2019-02-22 21:26:54 +01:00
David Given
a77925fe64 Replace the complicated sampler with 10 lines of Verilog; the hardware should 
now be able to handle any length of transition. And it's simpler.
 2019-02-22 20:01:34 +01:00
David Given
2527ac2ce9 Initial support for twin drives and 5.25" drives. 2019-02-11 23:43:44 +01:00
David Given
65315f4603 Take out the UART --- it's too much hassle. 2019-02-09 23:02:05 +01:00
David Given
e6a424d17a Abruptly realise that the capture logic was completely missing transitions too 
big to time; so, redesign it. Now the longest transition is 0xfe ticks and a
pulse is inserted if it's too long. Capture is way more robust now and the
resulting pulsetrain is a solid 198ms; and I wrote my first readable disk! (A
PC HD disk. Sadly, writing to the Brother didn't work.)
 2018-10-17 00:26:33 +02:00
David Given
99e222d012 Change the record mechanism to use an upcounter, not a timer. 2018-10-13 16:54:51 +02:00
David Given
aa7d420754 Start work on an autocalibrator to detect precompensation, but something's gone 
wrong and our reads are all bunk.
 2018-10-13 12:04:37 +02:00
David Given
b46d55cc07 The USB capture/replay interface now uses timestamps rather than intervals; 
this makes the hardware considerably simpler and more reliable (as I don't need
to spend time resetting the timers between pulses). Still doesn't help writes,
though. Simplify and improve clock detection; add an abortive attempt at an FM
decoder (turns out that the Brother doesn't use FM).
 2018-10-13 01:19:17 +02:00
David Given
1c0cc1f831 Rewrite the pulse replay logic to be, maybe, more reliable? Add lots of decoder 
debugging.
 2018-10-10 22:32:58 +02:00
David Given
443082f3c4 Written my first data --- it's kinda garbled, but there's definitely sectors in 
there!
 2018-10-06 23:30:14 +02:00
David Given
30271d7e95 Just enough writing works to utterly destroy tracks now. 2018-10-06 23:01:24 +02:00
David Given
8f1cef48b1 Realise that the weird data dropouts were due to a stray capacitor on the 
board... so remove it. Better now. Also realise that PSoC Creator lies to you
about clocks, so adjust the sample clock to be derivable from the USB clock,
making it both the right frequency and much more accurate --- decode success is
dramatically improved (presumably due to less jitter). Redesign the capture
logic to use a timer; simpler now.
 2018-10-06 18:32:57 +02:00
David Given
74d051dff3 Start sketching out the write code; attempt to make more robust in the face of 
the weird data dropouts.
 2018-10-06 13:47:34 +02:00
David Given
bf3e689708 Sketch out the replay logic, although it's not connected to anything yet. 2018-10-05 23:42:32 +02:00
David Given
d6b71beacf Reduced the sampling rate to 8MHz; 16MHz means that on a 720kB disk some 
samples are more than 128 ticks apart! Doubled the settling time to make reads
more reliable; added disk change logic to rehome the disk when you replace
floppies.
 2018-10-05 22:58:56 +02:00
David Given
fccabb3266 Add back in the hacky output file, for testing; replace the capture logic with 
an upcounter, and replace the pulse-in-high-bit stuff.
 2018-10-03 19:45:27 +02:00
David Given
a8738915e9 You can now read complete disk images into a database file. 2018-10-03 00:03:50 +02:00
David Given
841c1ed516 Attempt to capture rollover events --- don't think it works. Add a basic 
command processor.
 2018-10-02 23:03:07 +02:00
David Given
913829afbb Discover timers; drastically simplify and betterify everything. 2018-10-02 00:17:37 +02:00
David Given
51cb1ae785 We just read our first floppy! Turns out the secret is to, once again, remove 
C7 from the board as it's preventing the READ DATA line showing anything.
 2018-10-01 23:30:51 +02:00
David Given
4e19882d76 Archival checkin of messed-about non-working code to actually read data from 
disk. Something's wrong with the DMA; requesting a transfer every 2us with a TD
size of 64 bytes is somehow leading to an nrq interrupt every 8us. Mysterious.
 2018-09-30 01:13:39 +02:00
David Given
c174e5cafe You can now measure the rotation speed from the interval between index pulses. 2018-09-29 16:37:04 +02:00
David Given
026842b8a4 There's a seek command now, which might even work. 2018-09-29 14:51:01 +02:00
David Given
d06e201933 Finally figure out the secrets of WCID, so we don't need a signed driver to do 
raw endpoints. Hurrah! Rip out the CDC stuff in favour of them.
 2018-09-26 00:37:19 +02:00
David Given
755ae2950d Attempt to DMA data gibberish data from a fake acquisition unit and send it out 
over USB.
 2018-09-23 02:05:20 +02:00
David Given
9d00a1e5ea Bolt on USB UART. 2018-09-22 22:08:49 +02:00
David Given
a59c764dc5 Initial project boilerplate. 2018-09-22 21:44:33 +02:00