Merge pull request #112 from davidgiven/fixing

Rework the sequencer completely, because bizarrely writing disks just stopped working
Add missing files.
2025-10-24 11:11:02 -07:00 · 2019-11-29 22:02:44 +01:00 · 2019-11-29 18:49:22 +01:00 · 2019-11-25 20:54:13 +01:00 · 2019-11-25 20:52:13 +01:00 · 2019-11-24 15:14:32 +01:00
18 changed files with 1351 additions and 2159 deletions
--- a/FluxEngine.cydsn/CortexM3/ARM_GCC_541/Release/FluxEngine.hex
+++ b/FluxEngine.cydsn/CortexM3/ARM_GCC_541/Release/FluxEngine.hex
@@ -1,214 +1,214 @@
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@@ -4615,12 +4615,12 @@
 :0200000490105A
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 :00000001FF
--- a/FluxEngine.cydsn/FIFOout/API/c.c
+++ b/FluxEngine.cydsn/FIFOout/API/c.c
@@ -0,0 +1,29 @@
+#include "cyfitter_cfg.h"
+#include "cydevice_trm.h"
+#include "cyfitter.h"
+#include "`$INSTANCE_NAME`_h.h"
+
+void `$INSTANCE_NAME`_Start()
+{
+   `$INSTANCE_NAME`_Init();
+}    
+
+void `$INSTANCE_NAME`_Stop()
+{
+    `$INSTANCE_NAME`_Disable();
+}
+
+void `$INSTANCE_NAME`_Init()
+{    
+    `$INSTANCE_NAME`_Enable();
+    
+}
+void `$INSTANCE_NAME`_Enable()
+{
+}
+
+void `$INSTANCE_NAME`_Disable()
+{
+}
+
+/* [] END OF FILE */
--- a/FluxEngine.cydsn/FIFOout/API/h.h
+++ b/FluxEngine.cydsn/FIFOout/API/h.h
@@ -0,0 +1,50 @@
+#if !defined(`$INSTANCE_NAME`_H)
+#define `$INSTANCE_NAME`_H
+
+#include "cytypes.h"
+#include "cyfitter.h"
+#include "CyLib.h" 
+
+#define `$INSTANCE_NAME`_FIFO_PTR	         ((reg8 *) `$INSTANCE_NAME`_dp__F0_REG)
+
+    /* Macros to clear DP FIFOs.*/
+#define `$INSTANCE_NAME`_CLEAR do { \
+    CY_SET_XTND_REG8(\
+        ((reg8 *) `$INSTANCE_NAME`_dp__DP_AUX_CTL_REG), 0x01u | \
+        CY_GET_XTND_REG8(((reg8 *) `$INSTANCE_NAME`_dp__DP_AUX_CTL_REG)));\
+    CY_SET_XTND_REG8(\
+        ((reg8 *) `$INSTANCE_NAME`_dp__DP_AUX_CTL_REG), 0xfeu & \
+        CY_GET_XTND_REG8(((reg8 *) `$INSTANCE_NAME`_dp__DP_AUX_CTL_REG)));\
+    } while(0)
+
+/* Macros to set FIFO level mode. See the TRM for details */
+#define `$INSTANCE_NAME`_SET_LEVEL_NORMAL \
+    CY_SET_XTND_REG8(\
+        ((reg8 *) `$INSTANCE_NAME`_dp__DP_AUX_CTL_REG), 0xfbu & \
+        CY_GET_XTND_REG8(((reg8 *) `$INSTANCE_NAME`_dp__DP_AUX_CTL_REG)))
+#define `$INSTANCE_NAME`_SET_LEVEL_MID \
+    CY_SET_XTND_REG8(\
+        ((reg8 *) `$INSTANCE_NAME`_dp__DP_AUX_CTL_REG), 0x04u | \
+        CY_GET_XTND_REG8(((reg8 *) `$INSTANCE_NAME`_dp__DP_AUX_CTL_REG)))
+
+/* Macros to set FIFO to single-buffer mode. */
+#define `$INSTANCE_NAME`_SINGLE_BUFFER_SET \
+    CY_SET_XTND_REG8(\
+        ((reg8 *) `$INSTANCE_NAME`_dp__DP_AUX_CTL_REG), 0x01u | \
+        CY_GET_XTND_REG8(((reg8 *) `$INSTANCE_NAME`_dp__DP_AUX_CTL_REG)))
+
+/* Macros to return the FIFO to normal mode. */
+#define `$INSTANCE_NAME`_SINGLE_BUFFER_UNSET \
+    CY_SET_XTND_REG8(\
+        ((reg8 *) `$INSTANCE_NAME`_dp__DP_AUX_CTL_REG), 0xfeu & \
+        CY_GET_XTND_REG8(((reg8 *) `$INSTANCE_NAME`_dp__DP_AUX_CTL_REG)))
+    
+void `$INSTANCE_NAME`_Enable();
+void `$INSTANCE_NAME`_Disable();
+void `$INSTANCE_NAME`_Start();
+void `$INSTANCE_NAME`_Stop();
+void `$INSTANCE_NAME`_Init();
+
+#endif
+
+/* [] END OF FILE */
--- a/FluxEngine.cydsn/FIFOout/FIFOout.cysym
+++ b/FluxEngine.cydsn/FIFOout/FIFOout.cysym
--- a/FluxEngine.cydsn/FIFOout/FIFOout.v
+++ b/FluxEngine.cydsn/FIFOout/FIFOout.v
@@ -0,0 +1,168 @@
+
+//`#start header` -- edit after this line, do not edit this line
+`include "cypress.v"
+//`#end` -- edit above this line, do not edit this line
+// Generated on 11/16/2017 at 15:44
+// Component: FIFOout
+module FIFOout (
+    input req,
+	input clk,
+    output [7:0] d,
+	output drq,
+	output empty,
+    output ack
+);
+
+//`#start body` -- edit after this line, do not edit this line
+
+/* Reads from the FIFO are done based on the FIFO being not empty. */
+ 
+wire [7:0] po;
+assign d = po;
+
+localparam STATE_WAITFORREQ    = 1'b0;
+localparam STATE_READ          = 1'b1;
+
+reg state;
+reg oldreq;
+
+assign ack = (state != STATE_READ);
+
+always @(posedge clk)
+begin
+    case (state)
+        STATE_WAITFORREQ:
+        begin
+            if (!empty)
+            begin
+                if (req && !oldreq)
+                begin
+                    state <= STATE_READ;
+                end
+                oldreq <= req;
+            end
+        end
+        
+        STATE_READ:
+        begin
+            state <= STATE_WAITFORREQ;
+        end
+    endcase
+end
+            
+cy_psoc3_dp #(.cy_dpconfig(
+{
+    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
+    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
+    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
+    `CS_CMP_SEL_CFGA, /*CFGRAM0: STATE_WAITFORREQ*/
+    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
+    `CS_SHFT_OP_PASS, `CS_A0_SRC___F0, `CS_A1_SRC_NONE,
+    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
+    `CS_CMP_SEL_CFGA, /*CFGRAM1: STATE_LOAD*/
+    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
+    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
+    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
+    `CS_CMP_SEL_CFGA, /*CFGRAM2:           */
+    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
+    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
+    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
+    `CS_CMP_SEL_CFGA, /*CFGRAM3:           */
+    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
+    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
+    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
+    `CS_CMP_SEL_CFGA, /*CFGRAM4:           */
+    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
+    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
+    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
+    `CS_CMP_SEL_CFGA, /*CFGRAM5:           */
+    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
+    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
+    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
+    `CS_CMP_SEL_CFGA, /*CFGRAM6:           */
+    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
+    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
+    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
+    `CS_CMP_SEL_CFGA, /*CFGRAM7:           */
+    8'hFF, 8'h00,  /*CFG9:           */
+    8'hFF, 8'hFF,  /*CFG11-10:           */
+    `SC_CMPB_A1_D1, `SC_CMPA_A1_D1, `SC_CI_B_ARITH,
+    `SC_CI_A_ARITH, `SC_C1_MASK_DSBL, `SC_C0_MASK_DSBL,
+    `SC_A_MASK_DSBL, `SC_DEF_SI_0, `SC_SI_B_DEFSI,
+    `SC_SI_A_DEFSI, /*CFG13-12:           */
+    `SC_A0_SRC_ACC, `SC_SHIFT_SL, 1'h0,
+    1'h0, `SC_FIFO1_BUS, `SC_FIFO0_BUS,
+    `SC_MSB_DSBL, `SC_MSB_BIT0, `SC_MSB_NOCHN,
+    `SC_FB_NOCHN, `SC_CMP1_NOCHN,
+    `SC_CMP0_NOCHN, /*CFG15-14:           */
+    10'h00, `SC_FIFO_CLK__DP,`SC_FIFO_CAP_AX,
+    `SC_FIFO_LEVEL,`SC_FIFO_ASYNC,`SC_EXTCRC_DSBL,
+    `SC_WRK16CAT_DSBL /*CFG17-16:           */
+}
+)) dp(
+        /*  input                   */  .reset(1'b0),
+        /*  input                   */  .clk(clk),
+        /*  input   [02:00]         */  .cs_addr({2'b0, state}),
+        /*  input                   */  .route_si(1'b0),
+        /*  input                   */  .route_ci(1'b0),
+        /*  input                   */  .f0_load(1'b0),
+        /*  input                   */  .f1_load(1'b0),
+        /*  input                   */  .d0_load(1'b0),
+        /*  input                   */  .d1_load(1'b0),
+        /*  output                  */  .ce0(),
+        /*  output                  */  .cl0(),
+        /*  output                  */  .z0(),
+        /*  output                  */  .ff0(),
+        /*  output                  */  .ce1(),
+        /*  output                  */  .cl1(),
+        /*  output                  */  .z1(),
+        /*  output                  */  .ff1(),
+        /*  output                  */  .ov_msb(),
+        /*  output                  */  .co_msb(),
+        /*  output                  */  .cmsb(),
+        /*  output                  */  .so(),
+        /*  output                  */  .f0_bus_stat(drq), // not full
+        /*  output                  */  .f0_blk_stat(empty), // empty
+        /*  output                  */  .f1_bus_stat(),
+        /*  output                  */  .f1_blk_stat(),
+        
+        /* input                    */  .ci(1'b0),     // Carry in from previous stage
+        /* output                   */  .co(),// Carry out to next stage
+        /* input                    */  .sir(1'b0),    // Shift in from right side
+        /* output                   */  .sor(),        // Shift out to right side
+        /* input                    */  .sil(1'b0),    // Shift in from left side
+        /* output                   */  .sol(),        // Shift out to left side
+        /* input                    */  .msbi(1'b0),   // MSB chain in
+        /* output                   */  .msbo(),       // MSB chain out
+        /* input [01:00]            */  .cei(2'b0),    // Compare equal in from prev stage
+        /* output [01:00]           */  .ceo(),        // Compare equal out to next stage
+        /* input [01:00]            */  .cli(2'b0),    // Compare less than in from prv stage
+        /* output [01:00]           */  .clo(),        // Compare less than out to next stage
+        /* input [01:00]            */  .zi(2'b0),     // Zero detect in from previous stage
+        /* output [01:00]           */  .zo(),         // Zero detect out to next stage
+        /* input [01:00]            */  .fi(2'b0),     // 0xFF detect in from previous stage
+        /* output [01:00]           */  .fo(),         // 0xFF detect out to next stage
+        /* input [01:00]            */  .capi(2'b0),   // Software capture from previous stage
+        /* output [01:00]           */  .capo(),       // Software capture to next stage
+        /* input                    */  .cfbi(1'b0),   // CRC Feedback in from previous stage
+        /* output                   */  .cfbo(),       // CRC Feedback out to next stage
+        /* input [07:00]            */  .pi(8'b0),     // Parallel data port
+        /* output [07:00]           */  .po(po)       // Parallel data port
+);
+
+//`#end` -- edit above this line, do not edit this line
+endmodule
+//`#start footer` -- edit after this line, do not edit this line
+//`#end` -- edit above this line, do not edit this line
+
+
+
+
+
+
+
+
+
+
+
+
--- a/FluxEngine.cydsn/FluxEngine.cydwr
+++ b/FluxEngine.cydsn/FluxEngine.cydwr
@@ -28,6 +28,30 @@
        <Data key="sync_with_bus_clk" value="True" />
        <Data key="user_set_domain" value="False" />
      </Group>
+      <Group key="1a7e8637-3b6b-4e84-839c-0dfc18fdaf5b">
+        <Data key="check_tolerance" value="True" />
+        <Data key="clock_version" value="v1" />
+        <Data key="derive_type" value="NAMED_DIVIDER" />
+        <Data key="desired_freq" value="0" />
+        <Data key="desired_unit" value="15" />
+        <Data key="divider" value="0" />
+        <Data key="domain" value="DIGITAL" />
+        <Data key="enabled" value="True" />
+        <Data key="minus_accuracy" value="0.25" />
+        <Data key="minus_tolerance" value="5" />
+        <Data key="name" value="Clock_5" />
+        <Data key="named_src_direct_connect" value="True" />
+        <Data key="netlist_name" value="Clock_5" />
+        <Data key="placement" value="AUTO" />
+        <Data key="plus_accuracy" value="0.25" />
+        <Data key="plus_tolerance" value="5" />
+        <Data key="scope" value="LOCAL" />
+        <Data key="src_clk_id" value="75C2148C-3656-4d8a-846D-0CAE99AB6FF7" />
+        <Data key="src_clk_name" value="BUS_CLK" />
+        <Data key="start_on_reset" value="True" />
+        <Data key="sync_with_bus_clk" value="True" />
+        <Data key="user_set_domain" value="False" />
+      </Group>
      <Group key="4eef02b9-8ad1-43c4-85f1-b3335faa5fc4">
        <Data key="check_tolerance" value="True" />
        <Data key="clock_version" value="v1" />
@@ -609,6 +633,7 @@
  <Group key="DWRInstGuidMapping">
    <Group key="Clock">
      <Data key="0b2f9bbb-00ce-4115-a788-ffb9d046a9e5" value="Clock_4" />
+      <Data key="1a7e8637-3b6b-4e84-839c-0dfc18fdaf5b" value="Clock_5" />
      <Data key="4eef02b9-8ad1-43c4-85f1-b3335faa5fc4" value="Clock_3" />
      <Data key="06c4d5d4-f15f-4b29-a1d0-c24b2e38b1ec" value="CounterClock" />
      <Data key="24cd38f7-f472-4403-837f-86807c8f5333" value="PULSE_CLOCK" />
@@ -638,13 +663,14 @@
      <Data key="a5d987c6-e45b-45b9-ad93-656fab06d720" value="TRK00" />
      <Data key="a93ef5b3-00f4-42c0-8fad-0e275a7e2537" value="MOTEB" />
      <Data key="b8380fb7-fdb8-449f-bd8d-c4ca96cdf55a" value="DEBUG_PINS" />
+      <Data key="bc2e8987-db82-469c-bf6f-22fd3464cc70" value="DEBUG_PINS" />
      <Data key="bc5d52a1-1b25-4aa0-9ba9-3f81d122772f" value="DEBUG_PINS" />
      <Data key="beca5e2d-f70f-4900-a4db-7eca1ed3126e/8b77a6c4-10a0-4390-971c-672353e2a49c" value="USBFS_Dm" />
      <Data key="beca5e2d-f70f-4900-a4db-7eca1ed3126e/618a72fc-5ddd-4df5-958f-a3d55102db42" value="USBFS_Dp" />
      <Data key="c5367cde-21d5-4866-9a32-d16abfea0c61" value="WPT" />
      <Data key="d19368c5-6855-41bb-a9ff-808938abef00" value="INDEX" />
      <Data key="e9f14b5a-b2bf-49b8-98f3-d7b5a43ace8d" value="DRVSB" />
-      <Data key="e851a3b9-efb8-48be-bbb8-b303b216c393" value="LED" />
+      <Data key="e851a3b9-efb8-48be-bbb8-b303b216c393" value="LED_PIN" />
      <Data key="e51063a9-4fad-40c7-a06b-7cc4b137dc18" value="DSKCHG" />
      <Data key="ea7ee228-8b3f-426c-8bb8-cd7a81937769" value="DIR" />
      <Data key="ed092b9b-d398-4703-be89-cebf998501f6" value="UartTx" />
@@ -3859,6 +3885,32 @@
        <Data key="Port Format" value="2,3" />
      </Group>
    </Group>
+    <Group key="bc2e8987-db82-469c-bf6f-22fd3464cc70">
+      <Group key="0">
+        <Data key="Port Format" value="0,0" />
+      </Group>
+      <Group key="1">
+        <Data key="Port Format" value="0,1" />
+      </Group>
+      <Group key="2">
+        <Data key="Port Format" value="0,2" />
+      </Group>
+      <Group key="3">
+        <Data key="Port Format" value="0,3" />
+      </Group>
+      <Group key="4">
+        <Data key="Port Format" value="0,4" />
+      </Group>
+      <Group key="5">
+        <Data key="Port Format" value="0,5" />
+      </Group>
+      <Group key="6">
+        <Data key="Port Format" value="0,6" />
+      </Group>
+      <Group key="7">
+        <Data key="Port Format" value="0,7" />
+      </Group>
+    </Group>
    <Group key="bc5d52a1-1b25-4aa0-9ba9-3f81d122772f">
      <Group key="0">
        <Data key="Port Format" value="0,5" />
@@ -3914,7 +3966,7 @@
    </Group>
    <Group key="fbd1f839-40f9-498e-a48b-5f3048ea5c3d/52f31aa9-2f0a-497d-9a1f-1424095e13e6">
      <Group key="0">
-        <Data key="Port Format" value="2,5" />
+        <Data key="Port Format" value="12,7" />
      </Group>
    </Group>
    <Group key="fede1767-f3fd-4021-b3d7-8f9d88f36f9b">
--- a/FluxEngine.cydsn/FluxEngine.cyprj
+++ b/FluxEngine.cydsn/FluxEngine.cyprj
--- a/FluxEngine.cydsn/UdbSequencer/UdbSequencer.cysym
+++ b/FluxEngine.cydsn/UdbSequencer/UdbSequencer.cysym
--- a/FluxEngine.cydsn/Sequencer/Sequencer.v
+++ b/FluxEngine.cydsn/Sequencer/Sequencer.v
@@ -0,0 +1,101 @@
+
+//`#start header` -- edit after this line, do not edit this line
+`include "cypress.v"
+//`#end` -- edit above this line, do not edit this line
+// Generated on 11/24/2019 at 17:25
+// Component: Sequencer
+module Sequencer (
+	output req, /* request new data on leading edge */
+	output wdata,
+    output [2:0] debug_state,
+	input clock,
+	input dataclock, /* incoming data on leading edge */
+	input [7:0] opcode,
+    input index,
+    input sampleclock,
+    input reset
+);
+
+//`#start body` -- edit after this line, do not edit this line
+
+localparam STATE_IDLE = 0;
+localparam STATE_LOAD = 1;
+localparam STATE_WAITING = 2;
+localparam STATE_PULSING = 3;
+localparam STATE_INDEXING = 4;
+
+localparam OPCODE_PULSE = 8'h80;
+localparam OPCODE_INDEX = 8'h81;
+
+reg [2:0] state;
+reg [6:0] countdown;
+
+assign req = (state == STATE_LOAD);
+assign wdata = (state == STATE_PULSING);
+assign debug_state = state;
+
+reg olddataclock;
+wire dataclocked;
+always @(posedge clock) olddataclock <= dataclock;
+assign dataclocked = !olddataclock && dataclock;
+
+reg oldsampleclock;
+wire sampleclocked;
+always @(posedge clock) oldsampleclock <= sampleclock;
+assign sampleclocked = !oldsampleclock && sampleclock;
+
+reg oldindex;
+wire indexed;
+always @(posedge clock) oldindex <= index;
+assign indexed = !oldindex && index;
+
+always @(posedge clock)
+begin
+    if (reset)
+    begin
+        state <= STATE_IDLE;
+        countdown <= 0;
+    end
+    else
+        case (state)
+            STATE_IDLE:
+                state <= STATE_LOAD;
+            
+            STATE_LOAD:
+                if (dataclocked)
+                    case (opcode)
+                        OPCODE_PULSE:
+                            state <= STATE_PULSING;
+                        
+                        OPCODE_INDEX:
+                            state <= STATE_INDEXING;
+                        
+                        default:
+                        begin
+                            countdown <= opcode[6:0];
+                            state <= STATE_WAITING;
+                        end
+                    endcase
+            
+            STATE_WAITING:
+                if (sampleclocked)
+                begin
+                    if (countdown == 0)
+                        state <= STATE_LOAD;
+                    else
+                        countdown <= countdown - 1;
+                end
+            
+            STATE_PULSING:
+                state <= STATE_LOAD;
+            
+            STATE_INDEXING:
+                if (indexed)
+                    state <= STATE_LOAD;
+        endcase
+end
+
+//`#end` -- edit above this line, do not edit this line
+endmodule
+//`#start footer` -- edit after this line, do not edit this line
+//`#end` -- edit above this line, do not edit this line
--- a/FluxEngine.cydsn/TopDesign/TopDesign.cysch
+++ b/FluxEngine.cydsn/TopDesign/TopDesign.cysch
--- a/FluxEngine.cydsn/UdbSequencer/UdbSequencer.cyudb
+++ b/FluxEngine.cydsn/UdbSequencer/UdbSequencer.cyudb
--- a/FluxEngine.cydsn/main.c
+++ b/FluxEngine.cydsn/main.c
@@ -291,7 +291,6 @@ static void cmd_read(struct read_frame* f)

    /* Wait for the beginning of a rotation. */
        
-    print("wait");
    index_irq = false;
    while (!index_irq)
        ;
@@ -306,7 +305,6 @@ static void cmd_read(struct read_frame* f)
    dma_underrun = false;
    int count = 0;
    SAMPLER_CONTROL_Write(0); /* !reset */
-    CAPTURE_CONTROL_Write(1);
    CyDmaChSetInitialTd(dma_channel, td[dma_writing_to_td]);
    CyDmaClearPendingDrq(dma_channel);
    CyDmaChEnable(dma_channel, 1);
@@ -366,7 +364,6 @@ static void cmd_read(struct read_frame* f)
        dma_reading_from_td = NEXT_BUFFER(dma_reading_from_td);
    }
 abort:;
-    CAPTURE_CONTROL_Write(0);
    CyDmaChSetRequest(dma_channel, CY_DMA_CPU_TERM_CHAIN);
    while (CyDmaChGetRequest(dma_channel))
        ;
@@ -412,25 +409,28 @@ static void init_replay_dma(void)

        CyDmaTdSetConfiguration(td[i], BUFFER_SIZE, td[nexti],
            CY_DMA_TD_INC_SRC_ADR | SEQUENCER_DMA__TD_TERMOUT_EN);
-        CyDmaTdSetAddress(td[i], LO16((uint32)&dma_buffer[i]), LO16((uint32)&SEQUENCER_DATAPATH_F0_REG));
+        CyDmaTdSetAddress(td[i], LO16((uint32)&dma_buffer[i]), LO16((uint32)REPLAY_FIFO_FIFO_PTR));
    }    
 }

 static void cmd_write(struct write_frame* f)
 {
+    print("cmd_write");
+    
    if (f->bytes_to_write % FRAME_SIZE)
    {
        send_error(F_ERROR_INVALID_VALUE);
        return;
    }
    
+    SEQUENCER_CONTROL_Write(1); /* put the sequencer into reset */
+
    SIDE_REG_Write(f->side);
-    SEQUENCER_CONTROL_Write(1); /* reset */
    {
-        uint8_t i = CyEnterCriticalSection();
-        SEQUENCER_DATAPATH_F0_SET_LEVEL_NORMAL;
-        SEQUENCER_DATAPATH_F0_CLEAR;
-        SEQUENCER_DATAPATH_F0_SINGLE_BUFFER_UNSET;
+        uint8_t i = CyEnterCriticalSection();        
+        REPLAY_FIFO_SET_LEVEL_NORMAL;
+        REPLAY_FIFO_CLEAR;
+        REPLAY_FIFO_SINGLE_BUFFER_UNSET;
        CyExitCriticalSection(i);
    }
    seek_to(current_track);    
@@ -555,7 +555,7 @@ abort:
        CyDmaChDisable(dma_channel);
    }
    
-    //debug("p=%d cr=%d cw=%d f=%d l=%d w=%d index=%d underrun=%d", packets, count_read, count_written, finished, listening, writing, index_irq, dma_underrun);
+    print("p=%d cr=%d cw=%d f=%d w=%d index=%d underrun=%d", packets, count_read, count_written, finished, writing, index_irq, dma_underrun);
    if (!finished)
    {
        while (count_read < packets)
@@ -573,6 +573,7 @@ abort:
    }
    
    deinit_dma();
+    print("write finished");
    
    if (dma_underrun)
    {
--- a/doc/disk-brother.md
+++ b/doc/disk-brother.md
@@ -129,8 +129,8 @@ reverse engineered it to find out.

 Standard Linux mtools will access the filesystem image and allow you to move
 files in and out. However, you'll need to change the media type bytes at
-offsets 0x015 and 0x100 from 0x58 to 0xf0 before mtools will touch it. Once
-done, this will work:
+offsets 0x015 and 0x100 from 0x58 to 0xf0 before mtools will touch it. The
+supplied `brother240tool` will do this. Once done, this will work:

 ```
 mdir -i brother.img
--- a/doc/technical.md
+++ b/doc/technical.md
@@ -123,8 +123,12 @@ admittedly expensive.)
    sheet](http://www.bitsavers.org/pdf/mitsubishi/floppy/M4851/TJ2-G30211A_M4851_DSHH_48TPI_OEM_Manual_Nov83.pdf):
    the equivalent data sheet for a representative 5.25" drive.

+  - [The DRG Business Machines YD-174 manual](https://electrickery.hosting.philpem.me.uk/comp/divcomp/doc/YE_Data_YD-174_8inchFloppyDriveTechnicalManual.pdf):
+	the equivalent manual (data sheets hadn't been invented then) for a
+	representative 8" drive.
+
  - [KryoFlux stream file
    documentation](https://www.kryoflux.com/download/kryoflux_stream_protocol_rev1.1.pdf):
    the format of KryoFlux stream files (partially supported by FluxEngine)

-  
+  
--- a/mkninja.sh
+++ b/mkninja.sh
@@ -233,6 +233,13 @@ buildsimpleprogram brother120tool \
    libemu.a \
    libfmt.a \

+buildsimpleprogram brother240tool \
+	-Idep/emu \
+    tools/brother240tool.cc \
+    libbackend.a \
+    libemu.a \
+    libfmt.a \
+
 runtest bitaccumulator-test tests/bitaccumulator.cc
 runtest bytes-test          tests/bytes.cc
 runtest compression-test    tests/compression.cc
--- a/src/fe-erase.cc
+++ b/src/fe-erase.cc
@@ -3,7 +3,7 @@
 #include "fluxmap.h"
 #include "writer.h"

-static FlagGroup flags;
+static FlagGroup flags { &writerFlags };

 int mainErase(int argc, const char* argv[])
 {
--- a/src/fe-rpm.cc
+++ b/src/fe-rpm.cc
@@ -8,7 +8,7 @@ static FlagGroup flags;
 static DataSpecFlag source(
    { "--source", "-s" },
    "source for data",
-    ":d=0");
+    ":d=0:t=0:s=0");

 int mainRpm(int argc, const char* argv[])
 {
--- a/tools/brother240tool.cc
+++ b/tools/brother240tool.cc
@@ -0,0 +1,56 @@
+#include "globals.h"
+#include "fmt/format.h"
+#include <fstream>
+
+static std::fstream inputFile;
+
+void syntax()
+{
+    std::cout << "Syntax: brother240tool <image>\n"
+                 "The disk image will be flipped from Brother to DOS format and back\n"
+                 "again.\n";
+    exit(0);
+}
+
+uint8_t getbyte(uint32_t offset)
+{
+    inputFile.seekg(offset, std::ifstream::beg);
+    return inputFile.get();
+}
+
+void putbyte(uint32_t offset, uint8_t value)
+{
+    inputFile.seekp(offset, std::ifstream::beg);
+    inputFile.put(value);
+}
+
+int main(int argc, const char* argv[])
+{
+    if (argc < 2)
+        syntax();
+    
+    inputFile.open(argv[1], std::ios::in | std::ios::out | std::ios::binary);
+    if (!inputFile.is_open())
+		Error() << fmt::format("cannot open input file '{}'", argv[1]);
+
+    uint8_t b1 = getbyte(0x015);
+    uint8_t b2 = getbyte(0x100);
+    if ((b1 == 0x58) && (b2 == 0x58))
+    {
+        std::cerr << "Flipping from Brother to DOS.\n";
+        putbyte(0x015, 0xf0);
+        putbyte(0x100, 0xf0);
+    }
+    else if ((b1 == 0xf0) && (b2 == 0xf0))
+    {
+        std::cerr << "Flipping from DOS to Brother.\n";
+        putbyte(0x015, 0x58);
+        putbyte(0x100, 0x58);
+    }
+    else
+        Error() << "Unknown image format.";
+
+    inputFile.close();
+    return 0;
+}
+
Author	SHA1	Message	Date
David Given	8ee6eed4dc	Merge pull request #112 from davidgiven/fixing Rework the sequencer completely, because bizarrely writing disks just stopped working	2019-11-29 22:02:44 +01:00
David Given	3094c5c919	Add missing files.	2019-11-29 18:49:22 +01:00
David Given	1e012699af	Clean up the Verilog a bit.	2019-11-25 20:54:13 +01:00
David Given	91d6e9aeb9	Rewrite the sequencer engine with a separate fifo component and a pure verilog sequencer --- much easier to understand. We can write disks again!	2019-11-25 20:52:13 +01:00
David Given	a40b26ff46	Archival checkin for trying to figure out why writes no longer work.	2019-11-24 15:14:32 +01:00
David Given	ebcb9c4bb0	Switch the output lines to open-drain drive low.	2019-11-24 02:06:45 +01:00
David Given	2520834b18	Add the brother240tool program.	2019-11-24 01:46:02 +01:00
David Given	a1f3087046	Add an 8" drive datasheet.	2019-11-24 01:45:43 +01:00
David Given	e9670e205e	Don't erroneously crash out if the t and s parameters are omitted from the rpm command.	2019-10-14 22:25:43 +02:00
David Given	658e2b7295	Properly initialise flags. Fixes: #109	2019-09-22 21:55:37 +02:00