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https://github.com/davidgiven/fluxengine.git
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88 lines
2.3 KiB
Verilog
88 lines
2.3 KiB
Verilog
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//`#start header` -- edit after this line, do not edit this line
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`include "cypress.v"
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//`#end` -- edit above this line, do not edit this line
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// Generated on 11/24/2019 at 17:25
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// Component: Sequencer
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module Sequencer (
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output req, /* request new data on leading edge */
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output wdata,
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output [2:0] debug_state,
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input clock,
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input dataclock, /* incoming data on leading edge */
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input [7:0] opcode,
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input index,
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input sampleclock,
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input reset
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);
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//`#start body` -- edit after this line, do not edit this line
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localparam STATE_LOAD = 0;
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localparam STATE_WRITING = 1;
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reg state;
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reg [5:0] countdown;
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reg pulsepending;
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assign req = (!reset && (state == STATE_LOAD));
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assign wdata = (!reset && (state == STATE_WRITING) && (countdown == 0) && pulsepending);
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assign debug_state = 0;
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reg olddataclock;
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wire dataclocked;
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always @(posedge clock) olddataclock <= dataclock;
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assign dataclocked = !olddataclock && dataclock;
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reg oldsampleclock;
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always @(posedge clock) oldsampleclock <= sampleclock;
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wire sampleclocked;
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assign sampleclocked = !oldsampleclock && sampleclock;
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reg oldindex;
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wire indexed;
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always @(posedge clock) oldindex <= index;
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assign indexed = !oldindex && index;
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always @(posedge clock)
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begin
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if (reset)
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begin
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state <= STATE_LOAD;
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countdown <= 0;
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pulsepending <= 0;
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end
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else
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begin
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case (state)
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STATE_LOAD:
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begin
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/* A posedge on dataclocked indicates that another opcode has
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* arrived. */
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if (dataclocked)
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begin
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pulsepending <= opcode[7];
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countdown <= opcode[5:0];
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state <= STATE_WRITING;
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end
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end
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STATE_WRITING:
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begin
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if (sampleclocked)
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begin
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if (countdown == 0)
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state <= STATE_LOAD;
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else
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countdown <= countdown - 1;
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end
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end
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endcase
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end
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end
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//`#end` -- edit above this line, do not edit this line
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endmodule
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//`#start footer` -- edit after this line, do not edit this line
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//`#end` -- edit above this line, do not edit this line
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