initial commit: setbit configured for TinyFPGA-BX

.gitignore

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+*.bin 
+*.txt 
+*.blif 
+*.out 
+*.vcd 
+*~ 
+*.json

.gitmodules

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+[submodule "ice-chips-verilog"]
+	path = ice-chips-verilog
+	url = https://github.com/TimRudy/ice-chips-verilog/
+[submodule "open-fpga-verilog-tutorial"]
+	path = open-fpga-verilog-tutorial
+	url = https://github.com/Obijuan/open-fpga-verilog-tutorial

01_setbit/Makefile

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+#-------------------------------------------------------
+#-- Default objective: to do simulation and synthesis
+#-------------------------------------------------------
+all: sim synth
+
+#----------------------------------------------
+#-- make sim
+#----------------------------------------------
+#-- Objective: testbench
+#----------------------------------------------
+sim: setbit_tb.vcd
+
+#-----------------------------------------------
+#-  make synth
+#-----------------------------------------------
+#-  Objective: synthesize and generate bitstream
+#-----------------------------------------------
+synth: setbit.bin
+
+#-------------------------------
+#-- Compilation & simulation
+#-------------------------------
+setbit_tb.vcd: setbit.v setbit_tb.v
+
+	#-- Compilation
+	iverilog -o setbit_tb.out setbit.v setbit_tb.v
+
+	#-- Simulation
+	./setbit_tb.out
+
+	#-- View simulation with gtkwave
+	gtkwave setbit_tb.vcd setbit_tb.gtkw &
+
+#------------------------------
+#-- Synthesis
+#------------------------------
+setbit.bin: setbit.v TinyFPGA-BX-pins.pcf
+
+	#-- Synthesis
+	yosys -p "synth_ice40 -top setbit -json setbit.json" setbit.v
+
+	#-- Place & route
+	nextpnr-ice40 --lp8k --json setbit.json --pcf TinyFPGA-BX-pins.pcf --asc setbit.txt
+
+	#-- Generate final binary, ready to download to FPGA
+	icepack setbit.txt setbit.bin
+
+
+#-- Clean
+clean:
+	rm -f *.bin *.txt *.blif *.out *.vcd *~ *.json
+
+.PHONY: all clean

01_setbit/TinyFPGA-BX-pins.pcf

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+###############################################################################
+#
+# TinyFPGA BX constraint file (.pcf)
+#
+###############################################################################
+#
+# Copyright (c) 2018, Luke Valenty
+# All rights reserved.
+# 
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+# 
+# 1. Redistributions of source code must retain the above copyright notice, this
+#    list of conditions and the following disclaimer.
+# 2. Redistributions in binary form must reproduce the above copyright notice,
+#    this list of conditions and the following disclaimer in the documentation
+#    and/or other materials provided with the distribution.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+# ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# The views and conclusions contained in the software and documentation are those
+# of the authors and should not be interpreted as representing official policies,
+# either expressed or implied, of the <project name> project. 
+#
+###############################################################################
+
+####
+# TinyFPGA BX information: https://github.com/tinyfpga/TinyFPGA-BX/
+####
+
+# Left side of board
+set_io -nowarn PIN_1 A2
+set_io -nowarn PIN_2 A1
+set_io -nowarn PIN_3 B1
+set_io -nowarn PIN_4 C2
+set_io -nowarn PIN_5 C1
+set_io -nowarn PIN_6 D2
+set_io -nowarn PIN_7 D1
+set_io -nowarn PIN_8 E2
+set_io -nowarn PIN_9 E1
+set_io -nowarn PIN_10 G2
+set_io -nowarn PIN_11 H1
+set_io -nowarn PIN_12 J1
+set_io -nowarn PIN_13 H2
+
+# Right side of board
+set_io -nowarn PIN_14 H9
+set_io -nowarn PIN_15 D9
+set_io -nowarn PIN_16 D8
+set_io -nowarn PIN_17 C9
+set_io -nowarn PIN_18 A9
+set_io -nowarn PIN_19 B8
+set_io -nowarn PIN_20 A8
+set_io -nowarn PIN_21 B7
+set_io -nowarn PIN_22 A7
+set_io -nowarn PIN_23 B6
+set_io -nowarn PIN_24 A6
+
+# SPI flash interface on bottom of board
+set_io -nowarn SPI_SS F7
+set_io -nowarn SPI_SCK G7
+set_io -nowarn SPI_IO0 G6
+set_io -nowarn SPI_IO1 H7
+set_io -nowarn SPI_IO2 H4
+set_io -nowarn SPI_IO3 J8
+
+# General purpose pins on bottom of board
+set_io -nowarn PIN_25 G1
+set_io -nowarn PIN_26 J3
+set_io -nowarn PIN_27 J4
+set_io -nowarn PIN_28 G9
+set_io -nowarn PIN_29 J9
+set_io -nowarn PIN_30 E8
+set_io -nowarn PIN_31 J2
+
+# LED
+set_io -nowarn LED B3
+
+# USB
+set_io -nowarn USBP B4
+set_io -nowarn USBN A4
+set_io -nowarn USBPU A3
+
+# 16MHz clock
+set_io -nowarn CLK B2 # input

01_setbit/setbit.v

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+//-----------------------------------------------------------------------------
+// setbit.v
+//-----------------------------------------------------------------------------
+//- (C) BQ, August 2015
+//- Written by Juan Gonzalez (Obijuan)
+//- GPL License
+//-----------------------------------------------------------------------------
+//-- "Hello world" component that simply sets its output to '1'
+//--
+//-- This is the simplest example that can be synthesized in the FPGA. Its 
+//-- main purpose is to verify that the entire compilation/synthesis/simulation
+//-- chain works correctly.
+//-----------------------------------------------------------------------------
+
+//-----------------------------------------------------------------------------
+//--  setbit module
+//--
+//-- We define our component as a module that has only one output, which we 
+//-- call LED. This pin is wired to '1'
+//-----------------------------------------------------------------------------
+module setbit(output LED);
+//wire LED; // this breaks iverilog
+
+	//-- Implementation: the pin is wired to '1'
+  assign LED = 1;
+
+endmodule
+
+

01_setbit/setbit_tb.gtkw

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+[timestart] 0
+@28
+setbit_tb.LED
+[pattern_trace] 1
+[pattern_trace] 0

01_setbit/setbit_tb.v

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+//-----------------------------------------------------------------------------
+//-- Testbench for setbit
+//-- (c) BQ August 2015
+//-- Written by Juan Gonzalez (obijuan)
+//-----------------------------------------------------------------------------
+//-- To simulate the component, it's necessary to create a test bench that
+//-- places the component, assigns values to the inputs, and checks the
+//-- outputs. In the case of the setbit component, it's very simple. It only
+//-- has one output, so we connect a wire to its output and verify that it's
+//-- actually set to 1.
+//-----------------------------------------------------------------------------
+
+//-- Testbench module
+module setbit_tb;
+
+//-- Cable to connect to the component that sets the bit to 1
+wire LED;
+
+//--Instantiate the component. Connected to wire LED
+setbit SB1 (
+  .LED (LED)
+);
+
+//-- Begin test
+initial begin
+
+	//-- Set the dumpfile
+	$dumpfile("setbit_tb.vcd");
+
+	//-- Dump everything into the dumpfile
+	$dumpvars(0, setbit_tb);
+
+	//-- Check if the wire is at 1 after 10 time units
+  //-- If it isn't, report a problem, but continue simulation
+  # 10 if (LED != 1)
+         $display("---->ERROR! Wire not at 1");
+			 else
+			   $display("Component OK!");
+
+  //-- End after 10 time units
+	# 10 $finish;
+end
+
+
+endmodule
+
+