udpated README

README.md

@@ -30,6 +30,10 @@ WSL works (with the caveat regarding programming described above), but a native
 
 ```pacman -S --noconfirm git make mingw-w64-ucrt-x86_64-yosys mingw-w64-ucrt-x86_64-nextpnr mingw-w64-ucrt-x86_64-icestorm mingw-w64-ucrt-x86_64-verilator```
 
+iverilog and gtkwave are also available if you need them (and gtkwave won't need an X server):
+
+```pacman -S --noconfirm git make mingw-w64-ucrt-x86_64-iverilog mingw-w64-ucrt-x86_64-gtkwave```
+
 To enable MSYS2 within VSCodium/VSCode terminals, [this](https://www.msys2.org/docs/ides-editors/) was useful.
 
 Verilator should be called with ```-CFLAGS -DVL_TIME_CONTEXT``` in the options to avoid link errors.  This won't break Verilator on Linux AFAICT.

gate/Makefile

@@ -59,7 +59,7 @@ all: $(PROJ).rpt $(PROJ).bin
 # Verilator simulation
 
 obj_dir/V%: %.cpp %.v
-	verilator -Wall --no-timing --cc --exe --build $^
+	verilator -CFLAGS -DVL_TIME_CONTEXT -Wall --no-timing --cc --exe --build $^
 
 verilate: obj_dir/V$(PROJ)
 	obj_dir/V$(PROJ)

gate/div3.v

@@ -17,6 +17,7 @@
 
 // cribbed from the baudrate generator here:
 // https://gitlab.alfter.us/salfter/68b50-dual-serial/-/raw/202e1a1a8720a4ca1aa0a76b04521c2a77b40721/68b50-dual-serial.pdf?inline=false
+// (which, in turn, can be found at https://www.onsemi.com/pub/Collateral/AND8001-D.PDF#page=3)
 
 module div3(clk, r, q);
     input wire clk;

thruwire/Makefile

@@ -59,7 +59,7 @@ all: $(PROJ).rpt $(PROJ).bin
 # Verilator simulation
 
 obj_dir/V%: %.cpp %.v
-	verilator -Wall --cc --exe --build $^
+	verilator -CFLAGS -DVL_TIME_CONTEXT -Wall --cc --exe --build $^
 
 verilate: obj_dir/V$(PROJ)
 	obj_dir/V$(PROJ)