34 lines
802 B
Verilog
34 lines
802 B
Verilog
`default_nettype none
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//`include "../verilog-6502/ALU.v"
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//`include "../verilog-6502/cpu.v"
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// look in pins.pcf for all the pin names on the TinyFPGA BX board
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module cputest (CLK, LED, USBPU);
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input wire CLK; // 16MHz clock
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output wire LED; // User/boot LED next to power LED
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output wire USBPU; // USB pull-up resistor
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// drive USB pull-up resistor to '0' to disable USB
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assign USBPU = 0;
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// The 6502
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wire [15:0] CPU_AB;
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reg [7:0] CPU_DI=8'hEA;
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wire [7:0] CPU_DO;
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wire CPU_WE;
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cpu ucpu(
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.clk(CLK),
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.reset(1'b1),
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.AB(CPU_AB),
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.DI(CPU_DI),
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.DO(CPU_DO),
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.WE(CPU_WE),
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.IRQ(1'b1),
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.NMI(1'b1),
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.RDY(1'b1)
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);
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assign LED=CPU_AB[15];
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endmodule
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