54 lines
1.4 KiB
Makefile
54 lines
1.4 KiB
Makefile
#-------------------------------------------------------
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#-- Default objective: to do simulation and synthesis
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#-------------------------------------------------------
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all: sim synth
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#----------------------------------------------
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#-- make sim
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#----------------------------------------------
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#-- Objective: testbench
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#----------------------------------------------
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sim: setbit_tb.vcd
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#-----------------------------------------------
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#- make synth
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#-----------------------------------------------
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#- Objective: synthesize and generate bitstream
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#-----------------------------------------------
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synth: setbit.bin
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#-------------------------------
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#-- Compilation & simulation
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#-------------------------------
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setbit_tb.vcd: setbit.v setbit_tb.v
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#-- Compilation
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iverilog -o setbit_tb.out setbit.v setbit_tb.v
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#-- Simulation
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./setbit_tb.out
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#-- View simulation with gtkwave
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gtkwave setbit_tb.vcd setbit_tb.gtkw &
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#------------------------------
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#-- Synthesis
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#------------------------------
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setbit.bin: setbit.v TinyFPGA-BX-pins.pcf
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#-- Synthesis
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yosys -p "synth_ice40 -top setbit -json setbit.json" setbit.v
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#-- Place & route
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nextpnr-ice40 --lp8k --json setbit.json --pcf TinyFPGA-BX-pins.pcf --asc setbit.txt
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#-- Generate final binary, ready to download to FPGA
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icepack setbit.txt setbit.bin
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#-- Clean
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clean:
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rm -f *.bin *.txt *.blif *.out *.vcd *~ *.json
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.PHONY: all clean
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