26 lines
522 B
Verilog
26 lines
522 B
Verilog
`default_nettype none
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`include "div3.v"
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module gate (CLK, PIN_24, LED, USBPU);
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input wire CLK;
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output wire PIN_24;
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output wire LED;
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output wire USBPU;
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// (TinyFPGA) drive USB pull-up resistor to '0' to disable USB
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assign USBPU = 0;
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localparam N=23;
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reg [N:0] counter=0;
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always @(posedge CLK)
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counter <= counter+1;
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assign LED=counter[N];
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// divide-by-3 counter from older version of 68b50-dual-serial
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div3 dut(.clk(counter[N]), .r(1), .q(PIN_24));
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endmodule
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