gate: simulate with Verilator

gate/Makefile

@@ -1,23 +1,81 @@
-all: sim synth
+# Makefile borrowed from https://github.com/cliffordwolf/icestorm/blob/master/examples/icestick/Makefile
+#
+# The following license is from the icestorm project and specifically applies to this file only:
+#
+#  Permission to use, copy, modify, and/or distribute this software for any
+#  purpose with or without fee is hereby granted, provided that the above
+#  copyright notice and this permission notice appear in all copies.
+#
+#  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+#  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+#  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+#  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+#  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+#  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+#  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 
-sim: gate_tb.vcd
+PROJ = gate
 
-synth: gate.bin
+PIN_DEF = tinyfpga-bx.pcf
+DEVICE = lp8k
+PACKAGE = cm81
+                                                                                                                                                     
+all: $(PROJ).rpt $(PROJ).bin
 
-prog: gate.bin
-	sudo tinyprog -p gate.bin
+# synthesis
 
-gate_tb.vcd: gate.v sim.v gate_tb.v
-	iverilog -o gate_tb.out gate.v gate_tb.v sim.v
-	./gate_tb.out
-	gtkwave gate_tb.vcd & # gate_tb.gtkw &
+%.json: %.v
+	yosys -p "synth_ice40 -top $(PROJ) -json $@" $<
 
-gate.bin: gate.v tinyfpga-bx.pcf
-	yosys -p "synth_ice40 -top gate -json gate.json" gate.v 
-	nextpnr-ice40 --lp8k --package cm81 --json gate.json --pcf tinyfpga-bx.pcf --asc gate.txt
-	icepack gate.txt gate.bin
+%.asc: %.json $(PIN_DEF)
+	nextpnr-ice40 --$(DEVICE) --package $(PACKAGE) --json $< --pcf $(PIN_DEF) --asc $@
+
+%.bin: %.asc
+	icepack $< $@
+
+%.rpt: %.asc
+	icetime -d $(DEVICE) -mtr $@ $<
+
+# testbench for Icarus Verilog
+
+%_tb: %_tb.v %.v
+	iverilog -o $@ $^
+
+%_tb.vcd: %_tb
+	vvp -N $< +vcd=$@
+
+%.blif: %.v
+	yosys -p 'synth_ice40 -top $(PROJ) -blif $@' $<
+
+%_syn.v: %.blif
+	yosys -p 'read_blif -wideports $^; write_verilog $@'
+
+%_syntb: %_tb.v %_syn.v
+	iverilog -o $@ $^ `yosys-config --datdir/ice40/cells_sim.v`
+
+%_syntb.vcd: %_syntb
+	vvp -N $< +vcd=$@
+
+# Verilator simulation
+
+obj_dir/V%: %.cpp %.v
+	verilator --no-timing --cc --exe --build $^
+
+verilate: obj_dir/V$(PROJ)
+	obj_dir/V$(PROJ)
+
+# device programming
+
+prog: $(PROJ).bin
+	tinyprog -p $<
+
+sudo-prog: $(PROJ).bin
+	@echo 'Executing prog as root!!!'
+	sudo tinyprog -p $<
 
 clean:
-	rm -f *.bin *.txt *.blif *.out *.vcd *~ *.json
+	rm -rf $(PROJ).blif $(PROJ).json $(PROJ).asc $(PROJ).rpt $(PROJ).bin obj_dir
+
+.SECONDARY:
+.PHONY: all prog clean
 
-.PHONY: all clean

gate/div3.v

@@ -1,3 +1,4 @@
+`default_nettype none
 `include "../ice-chips-verilog/includes/helper.v"
 `include "../ice-chips-verilog/source-7400/7404.v"
 `include "../ice-chips-verilog/source-7400/7408.v"
@@ -7,7 +8,10 @@
 // cribbed from the baudrate generator here:
 // https://gitlab.alfter.us/salfter/68b50-dual-serial/-/raw/202e1a1a8720a4ca1aa0a76b04521c2a77b40721/68b50-dual-serial.pdf?inline=false
 
-module div3(input wire clk, input wire r, output wire q);
+module div3(clk, r, q);
+    input wire clk;
+    input wire r;
+    output wire q;
 
     wire [1:0] U3_A;
     wire U3_Y;

gate/gate.cpp

@@ -0,0 +1,23 @@
+#include <stdio.h>
+#include <stdlib.h>
+#include "Vgate.h"
+#include "verilated.h"
+
+int main(int argc, char** argv) 
+{
+    Verilated::commandArgs(argc, argv);
+    Vgate *tb=new Vgate;
+
+    const int N=23; // copy from gate.v
+    for (int k=0; k<1<<(N+6); k++)
+    {
+        tb->CLK=k&1;
+        tb->eval();
+        if ((k&(1<<(N+1))-1)==0)
+        {
+            printf("k=%2d ", k>>(N+1));
+            printf("LED=%d ", tb->LED);
+            printf("PIN_24=%d \n", tb->PIN_24);
+        }
+    }
+}

gate/gate.v

@@ -1,6 +1,14 @@
+`default_nettype none
 `include "div3.v"
 
-module gate (input wire CLK, input wire PIN_22, input wire PIN_23, output wire PIN_24, output wire LED);
+module gate (CLK, PIN_24, LED, USBPU);
+    input wire CLK;
+    output wire PIN_24;
+    output wire LED;
+    output wire USBPU;
+
+    // (TinyFPGA) drive USB pull-up resistor to '0' to disable USB
+    assign USBPU = 0;
 
     localparam N=23;
     reg [N:0] counter=0;
@@ -10,18 +18,6 @@ module gate (input wire CLK, input wire PIN_22, input wire PIN_23, output wire P
 
     assign LED=counter[N];
 
-    localparam BLOCKS = 1;
-    localparam WIDTH_IN = 2;
-    wire [BLOCKS*WIDTH_IN-1:0] A;
-    wire Y;
-
-    assign A={counter[N], PIN_23};
-
-    // ttl_7400 #(.BLOCKS(BLOCKS), .WIDTH_IN(WIDTH_IN)) dut(
-    //   .A_2D(A),
-    //   .Y(PIN_24)
-    // );
-
     // divide-by-3 counter from older version of 68b50-dual-serial
 
     div3 dut(.clk(counter[N]), .r(1), .q(PIN_24));