fsm must run in 'slow' domain. alu must be combinatorial.
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Bastian Löher
@@ -15,29 +15,33 @@ def proc():
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clk = yield soc.slow_clk
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if prev_clk == 0 and prev_clk != clk:
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state = (yield soc.state)
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if state == 0:
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print("---- FETCH -----------------------")
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print(" pc={}".format((yield soc.pc)))
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print(" instr={:#032b}".format((yield soc.instr)))
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if state == 2:
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print("-- NEW CYCLE -----------------------")
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print(" F: LEDS = {:05b}".format((yield soc.leds)))
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print(" F: pc={}".format((yield soc.pc)))
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print(" F: instr={:#032b}".format((yield soc.instr)))
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if (yield soc.isALUreg):
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print(" ALUreg rd={} rs1={} rs2={} funct3={}".format(
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print(" ALUreg rd={} rs1={} rs2={} funct3={}".format(
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(yield soc.rdId), (yield soc.rs1Id), (yield soc.rs2Id),
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(yield soc.funct3)))
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if (yield soc.isALUimm):
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print(" ALUimm rd={} rs1={} imm={} funct3={}".format(
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print(" ALUimm rd={} rs1={} imm={} funct3={}".format(
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(yield soc.rdId), (yield soc.rs1Id), (yield soc.Iimm),
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(yield soc.funct3)))
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if (yield soc.isLoad):
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print(" LOAD")
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print(" LOAD")
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if (yield soc.isStore):
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print(" STORE")
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print(" STORE")
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if (yield soc.isSystem):
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print(" SYSTEM")
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print(" SYSTEM")
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break
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if state == 2:
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print("---- EXECUTE ---------------------")
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print(" LEDS = {:05b}".format((yield soc.leds)))
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print(" Writeback x{} = {:032b}".format((yield soc.rdId),
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if state == 4:
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print(" R: LEDS = {:05b}".format((yield soc.leds)))
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print(" R: rs1={}".format((yield soc.rs1)))
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print(" R: rs2={}".format((yield soc.rs2)))
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if state == 1:
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print(" E: LEDS = {:05b}".format((yield soc.leds)))
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print(" E: Writeback x{} = {:032b}".format((yield soc.rdId),
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(yield soc.writeBackData)))
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yield
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prev_clk = clk
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@@ -29,36 +29,47 @@ class SOC(Elaboratable):
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# ......|....|....|..|....|......|
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# add x1, x0, x0
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# rs2 rs1 add rd ALUREG
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# -> x1 = 0
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0b00000000000000000000000010110011,
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# addi x1, x1, 1
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# imm rs1 add rd ALUIMM
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# -> x1 = 1
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0b00000000000100001000000010010011,
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# addi x1, x1, 1
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# imm rs1 add rd ALUIMM
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# -> x1 = 2
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0b00000000000100001000000010010011,
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# addi x1, x1, 1
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# imm rs1 add rd ALUIMM
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# -> x1 = 3
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0b00000000000100001000000010010011,
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# addi x1, x1, 1
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# imm rs1 add rd ALUIMM
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# -> x1 = 4
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0b00000000000100001000000010010011,
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# add x2, x1, x0
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# rs2 rs1 add rd ALUREG
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# -> x2 = 4
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0b00000000000000001000000100110011,
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# add x2, x1, x0
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# add x3, x1, x2
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# rs2 rs1 add rd ALUREG
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# -> x3 = 8
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0b00000000001000001000000110110011,
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# srli x3, x3, 3
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# shamt rs1 sr rd ALUIMM
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# -> x3 = 1
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0b00000000001100011101000110010011,
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# slli x3, x3, 31
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# shamt rs1 sl rd ALUIMM
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# -> x3 = 0x80000000
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0b00000001111100011001000110010011,
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# srai x3, x3, 5
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# shamt rs1 sr rd ALUIMM
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# -> x3 = 0xfc000000
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0b01000000010100011101000110010011,
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# srli x1, x3, 26
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# shamt rs1 sr rd ALUIMM
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# -> x1 = 0x3f
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0b00000001101000011101000010010011,
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0b00000000000100000000000001110011 # S ebreak
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@@ -71,10 +82,10 @@ class SOC(Elaboratable):
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instr = Signal(32, reset=0b0110011)
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# Instruction memory initialised with above 'sequence'
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mem = Array([Signal(32, reset=x) for x in sequence])
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mem = Array([Signal(32, reset=x, name="mem") for x in sequence])
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# Register bank
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regs = Array([Signal(32) for x in range(32)])
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regs = Array([Signal(32, name="x"+str(x)) for x in range(32)])
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rs1 = Signal(32)
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rs2 = Signal(32)
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@@ -118,28 +129,28 @@ class SOC(Elaboratable):
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with m.Switch(funct3) as alu:
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with m.Case(0b000):
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m.d.slow += aluOut.eq(Mux(funct7[5] & instr[5],
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m.d.comb += aluOut.eq(Mux(funct7[5] & instr[5],
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(aluIn1 - aluIn2), (aluIn1 + aluIn2)))
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with m.Case(0b001):
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m.d.slow += aluOut.eq(aluIn1 << shamt)
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m.d.comb += aluOut.eq(aluIn1 << shamt)
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with m.Case(0b010):
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m.d.slow += aluOut.eq(aluIn1.as_signed() < aluIn2.as_signed())
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m.d.comb += aluOut.eq(aluIn1.as_signed() < aluIn2.as_signed())
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with m.Case(0b011):
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m.d.slow += aluOut.eq(aluIn1 < aluIn2)
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m.d.comb += aluOut.eq(aluIn1 < aluIn2)
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with m.Case(0b100):
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m.d.slow += aluOut.eq(aluIn1 ^ aluIn2)
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m.d.comb += aluOut.eq(aluIn1 ^ aluIn2)
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with m.Case(0b101):
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m.d.slow += aluOut.eq(Mux(
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m.d.comb += aluOut.eq(Mux(
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funct7[5],
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(aluIn1.as_signed() >> shamt), # arithmetic right shift
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(aluIn1.as_unsigned() >> shamt))) # logical right shift
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with m.Case(0b110):
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m.d.slow += aluOut.eq(aluIn1 | aluIn2)
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m.d.comb += aluOut.eq(aluIn1 | aluIn2)
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with m.Case(0b111):
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m.d.slow += aluOut.eq(aluIn1 & aluIn2)
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m.d.comb += aluOut.eq(aluIn1 & aluIn2)
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# Main state machine
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with m.FSM(reset="FETCH_INSTR") as fsm:
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with m.FSM(reset="FETCH_INSTR", domain="slow") as fsm:
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# Assign important signals to LEDS
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m.d.comb += self.leds.eq(Mux(isSystem, 31, (1 << fsm.state)))
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with m.State("FETCH_INSTR"):
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@@ -187,7 +198,11 @@ class SOC(Elaboratable):
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export(Iimm, "Iimm")
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export(funct3, "funct3")
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export(rdId, "rdId")
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export(rs1, "rs1")
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export(rs2, "rs2")
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export(writeBackData, "writeBackData")
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export(fsm.state, "state")
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export(writeBackEn, "writeBackEn")
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export(aluOut, "aluOut")
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export((1 << fsm.state), "state")
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return m
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