Simplify signals. Export operators as signals for simulation.
This commit is contained in:
Bastian Löher
@@ -19,8 +19,16 @@ def proc():
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print("LEDS = {:05b}".format((yield soc.leds)))
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if (yield soc.isALUreg):
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print("ALUreg rd={} rs1={} rs2={} funct3={}".format(
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(yield soc.rdId), (yield soc.rs1Id), (yield soc.rs2Id),
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(yield soc.funct3)))
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if (yield soc.isALUimm):
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print("ALUimm rd={} rs1={} imm={} funct3={}".format(
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(yield soc.rdId), (yield soc.rs1Id), (yield soc.Iimm),
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(yield soc.funct3)))
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if (yield soc.isLoad):
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print("LOAD")
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if (yield soc.isStore):
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print("STORE")
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if (yield soc.isSystem):
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print("SYSTEM")
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break
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@@ -30,6 +38,6 @@ def proc():
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sim.add_clock(1e-6)
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sim.add_sync_process(proc)
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with sim.write_vcd('bench.vcd'):
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with sim.write_vcd('bench.vcd', 'bench.gtkw', traces=soc.ports):
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# Let's run for a quite long time
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sim.run_until(2)
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sim.run_until(2, )
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@@ -1,3 +1,4 @@
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import sys
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from amaranth import *
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from clockworks import Clockworks
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@@ -8,6 +9,9 @@ class SOC(Elaboratable):
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self.leds = Signal(5)
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# Signals in this list can easily be plotted as vcd traces
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self.ports = []
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def elaborate(self, platform):
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m = Module()
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@@ -15,6 +19,7 @@ class SOC(Elaboratable):
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cw = Clockworks(slow=21)
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m.submodules.cw = cw
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# Instruction sequence to be executed
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sequence = [
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# 24 16 8 0
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# .......|.......|.......|.......|
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@@ -33,74 +38,44 @@ class SOC(Elaboratable):
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0b00000000000100000000000001110011 # S ebreak
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]
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# Signal declarations
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isALUreg = Signal()
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isALUimm = Signal()
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isBranch = Signal()
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isJALR = Signal()
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isJAL = Signal()
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isAUIPC = Signal()
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isLUI = Signal()
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isLoad = Signal()
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isStore = Signal()
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isSystem = Signal()
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Uimm, Iimm, Bimm, Simm, Jimm = [Signal(32) for _ in range(5)]
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rs1Id, rs2Id, rdId = [Signal(5) for _ in range(3)]
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funct3, funct7 = [Signal(3), Signal(7)]
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# Program counter
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pc = Signal(32)
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# Current instruction
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instr = Signal(32, reset=0b0110011)
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# Instruction memory initialised with above 'sequence'
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mem = Array([Signal(32, reset=x) for x in sequence])
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self.pc = pc
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self.instr = instr
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self.isALUreg = isALUreg
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self.isALUimm = isALUimm
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self.isSystem = isSystem
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self.rdId = rdId
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self.rs1Id = rs1Id
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self.rs2Id = rs2Id
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self.Iimm = Iimm
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self.funct3 = funct3
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# Opcode decoder
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m.d.comb += [
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isALUreg.eq(instr[0:7] == 0b0110011),
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isALUimm.eq(instr[0:7] == 0b0010011),
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isBranch.eq(instr[0:7] == 0b1100011),
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isJALR.eq( instr[0:7] == 0b1100111),
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isJAL.eq( instr[0:7] == 0b1101111),
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isAUIPC.eq( instr[0:7] == 0b0010111),
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isLUI.eq( instr[0:7] == 0b0110111),
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isLoad.eq( instr[0:7] == 0b0000011),
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isStore.eq( instr[0:7] == 0b0100011),
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isSystem.eq(instr[0:7] == 0b1110011),
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]
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isALUreg = (instr[0:7] == 0b0110011)
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isALUimm = (instr[0:7] == 0b0010011)
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isBranch = (instr[0:7] == 0b1100011)
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isJALR = (instr[0:7] == 0b1100111)
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isJAL = (instr[0:7] == 0b1101111)
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isAUIPC = (instr[0:7] == 0b0010111)
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isLUI = (instr[0:7] == 0b0110111)
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isLoad = (instr[0:7] == 0b0000011)
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isStore = (instr[0:7] == 0b0100011)
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isSystem = (instr[0:7] == 0b1110011)
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# Immediate format decoder
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m.d.comb += [
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Uimm.eq(Cat(Repl(0, 12), instr[12:32])),
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Iimm.eq(Cat(instr[20:31], Repl(instr[31], 21))),
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Simm.eq(Cat(instr[7:12], Cat(instr[25:31], Repl(instr[31], 21)))),
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Bimm.eq(Cat(0, Cat(instr[8:12], Cat(instr[25:31], Cat(
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instr[7], Repl(instr[31], 20)))))),
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Jimm.eq(Cat(0, Cat(instr[21:31], Cat(instr[20], Cat(
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instr[12:20], Repl(instr[31], 12))))))
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]
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Uimm = (Cat(Repl(0, 12), instr[12:32]))
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Iimm = (Cat(instr[20:31], Repl(instr[31], 21)))
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Simm = (Cat(instr[7:12], Cat(instr[25:31], Repl(instr[31], 21)))),
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Bimm = (Cat(0, Cat(instr[8:12], Cat(instr[25:31], Cat(
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instr[7], Repl(instr[31], 20))))))
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Jimm = (Cat(0, Cat(instr[21:31], Cat(instr[20], Cat(
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instr[12:20], Repl(instr[31], 12))))))
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# Register addresses decoder
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m.d.comb += [
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rs1Id.eq(instr[15:20]),
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rs2Id.eq(instr[20:25]),
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rdId.eq( instr[7:12])
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]
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rs1Id = (instr[15:20])
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rs2Id = (instr[20:25])
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rdId = ( instr[7:12])
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# Function code decdore
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m.d.comb += [
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funct3.eq(instr[12:15]),
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funct7.eq(instr[25:32])
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]
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funct3 = (instr[12:15])
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funct7 = (instr[25:32])
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# Fetch instruction and increase PC
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m.d.slow += [
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@@ -112,4 +87,28 @@ class SOC(Elaboratable):
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m.d.comb += self.leds.eq(Mux(isSystem, 31, Cat(isLoad, Cat(
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isStore, Cat(isALUimm, Cat(isALUreg, pc[0]))))))
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def export(signal, name):
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if type(signal) is not Signal:
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newsig = Signal(signal.shape(), name = name)
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m.d.comb += newsig.eq(signal)
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else:
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newsig = signal
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self.ports.append(newsig)
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setattr(self, name, newsig)
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# Export signals for simulation
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if platform is None:
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export(pc, "pc")
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export(instr, "instr")
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export(isALUreg, "isALUreg")
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export(isALUimm, "isALUimm")
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export(isLoad, "isLoad")
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export(isStore, "isStore")
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export(isSystem, "isSystem")
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export(rdId, "rdId")
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export(rs1Id, "rs1Id")
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export(rs2Id, "rs2Id")
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export(Iimm, "Iimm")
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export(funct3, "funct3")
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return m
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