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Update from Cat(a, Cat(b, Cat(c, d))) to Cat(a, b, c, d)

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This is supported, not sure since when, and makes the code a bit
more readable and less error-prone.
This commit is contained in:
Josuah Demangeon
2023-03-12 14:08:02 +01:00
parent 975f018a53
commit 7807bd61d9
7 changed files with 25 additions and 39 deletions
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12
04_instruction_decoder/soc.py
View File

@@ -62,11 +62,9 @@ class SOC(Elaboratable):
# Immediate format decoder
Uimm = (Cat(Repl(0, 12), instr[12:32]))
Iimm = (Cat(instr[20:31], Repl(instr[31], 21)))
Simm = (Cat(instr[7:12], Cat(instr[25:31], Repl(instr[31], 21)))),
Bimm = (Cat(0, Cat(instr[8:12], Cat(instr[25:31], Cat(
instr[7], Repl(instr[31], 20))))))
Jimm = (Cat(0, Cat(instr[21:31], Cat(instr[20], Cat(
instr[12:20], Repl(instr[31], 12))))))
Simm = (Cat(instr[7:12], instr[25:31], Repl(instr[31], 21))),
Bimm = (Cat(0, instr[8:12], instr[25:31], instr[7], Repl(instr[31], 20)))
Jimm = (Cat(0, instr[21:31], instr[20], instr[12:20], Repl(instr[31], 12)))
# Register addresses decoder
rs1Id = (instr[15:20])
@@ -84,8 +82,8 @@ class SOC(Elaboratable):
]
# Assign important signals to LEDS
m.d.comb += self.leds.eq(Mux(isSystem, 31, Cat(isLoad, Cat(
isStore, Cat(isALUimm, Cat(isALUreg, pc[0]))))))
m.d.comb += self.leds.eq(Mux(isSystem, 31,
Cat(isLoad, isStore, isALUimm, isALUreg, pc[0])))
# Export signals for simulation
def export(signal, name):

8
05_register_bank/soc.py
View File

@@ -70,11 +70,9 @@ class SOC(Elaboratable):
# Immediate format decoder
Uimm = (Cat(Repl(0, 12), instr[12:32]))
Iimm = (Cat(instr[20:31], Repl(instr[31], 21)))
Simm = (Cat(instr[7:12], Cat(instr[25:31], Repl(instr[31], 21)))),
Bimm = (Cat(0, Cat(instr[8:12], Cat(instr[25:31], Cat(
instr[7], Repl(instr[31], 20))))))
Jimm = (Cat(0, Cat(instr[21:31], Cat(instr[20], Cat(
instr[12:20], Repl(instr[31], 12))))))
Simm = (Cat(instr[7:12], instr[25:31], Repl(instr[31], 21))),
Bimm = (Cat(0, instr[8:12], instr[25:31], instr[7], Repl(instr[31], 20)))
Jimm = (Cat(0, instr[21:31], instr[20], instr[12:20], Repl(instr[31], 12)))
# Register addresses decoder
rs1Id = (instr[15:20])

8
06_alu/soc.py
View File

@@ -107,11 +107,9 @@ class SOC(Elaboratable):
# Immediate format decoder
Uimm = (Cat(Repl(0, 12), instr[12:32]))
Iimm = (Cat(instr[20:31], Repl(instr[31], 21)))
Simm = (Cat(instr[7:12], Cat(instr[25:31], Repl(instr[31], 21)))),
Bimm = (Cat(0, Cat(instr[8:12], Cat(instr[25:31], Cat(
instr[7], Repl(instr[31], 20))))))
Jimm = (Cat(0, Cat(instr[21:31], Cat(instr[20], Cat(
instr[12:20], Repl(instr[31], 12))))))
Simm = (Cat(instr[7:12], instr[25:31], Repl(instr[31], 21))),
Bimm = (Cat(0, instr[8:12], instr[25:31], instr[7], Repl(instr[31], 20)))
Jimm = (Cat(0, instr[21:31], instr[20], instr[12:20], Repl(instr[31], 12)))
# Register addresses decoder
rs1Id = (instr[15:20])

10
07_assembler/soc.py
View File

@@ -73,16 +73,14 @@ class SOC(Elaboratable):
# Immediate format decoder
Uimm = (Cat(Repl(0, 12), instr[12:32]))
Iimm = (Cat(instr[20:31], Repl(instr[31], 21)))
Simm = (Cat(instr[7:12], Cat(instr[25:31], Repl(instr[31], 21)))),
Bimm = (Cat(0, Cat(instr[8:12], Cat(instr[25:31], Cat(
instr[7], Repl(instr[31], 20))))))
Jimm = (Cat(0, Cat(instr[21:31], Cat(instr[20], Cat(
instr[12:20], Repl(instr[31], 12))))))
Simm = (Cat(instr[7:12], instr[25:31], Repl(instr[31], 21))),
Bimm = (Cat(0, instr[8:12], instr[25:31], instr[7], Repl(instr[31], 20)))
Jimm = (Cat(0, instr[21:31], instr[20], instr[12:20], Repl(instr[31], 12)))
# Register addresses decoder
rs1Id = (instr[15:20])
rs2Id = (instr[20:25])
rdId = ( instr[7:12])
rdId = (instr[7:12])
# Function code decdore
funct3 = (instr[12:15])

8
08_jumps/soc.py
View File

@@ -65,11 +65,9 @@ class SOC(Elaboratable):
# Immediate format decoder
Uimm = (Cat(Repl(0, 12), instr[12:32]))
Iimm = (Cat(instr[20:31], Repl(instr[31], 21)))
Simm = (Cat(instr[7:12], Cat(instr[25:31], Repl(instr[31], 21)))),
Bimm = (Cat(0, Cat(instr[8:12], Cat(instr[25:31], Cat(
instr[7], Repl(instr[31], 20))))))
Jimm = (Cat(0, Cat(instr[21:31], Cat(instr[20], Cat(
instr[12:20], Repl(instr[31], 12))))))
Simm = (Cat(instr[7:12], instr[25:31], Repl(instr[31], 21))),
Bimm = (Cat(0, instr[8:12], instr[25:31], instr[7], Repl(instr[31], 20)))
Jimm = (Cat(0, instr[21:31], instr[20], instr[12:20], Repl(instr[31], 12)))
# Register addresses decoder
rs1Id = (instr[15:20])

10
09_branches/soc.py
View File

@@ -67,16 +67,14 @@ class SOC(Elaboratable):
# Immediate format decoder
Uimm = (Cat(Repl(0, 12), instr[12:32]))
Iimm = (Cat(instr[20:31], Repl(instr[31], 21)))
Simm = (Cat(instr[7:12], Cat(instr[25:31], Repl(instr[31], 21)))),
Bimm = (Cat(0, Cat(instr[8:12], Cat(instr[25:31], Cat(
instr[7], Repl(instr[31], 20))))))
Jimm = (Cat(0, Cat(instr[21:31], Cat(instr[20], Cat(
instr[12:20], Repl(instr[31], 12))))))
Simm = (Cat(instr[7:12], instr[25:31], Repl(instr[31], 21))),
Bimm = (Cat(0, instr[8:12], instr[25:31], instr[7], Repl(instr[31], 20)))
Jimm = (Cat(0, instr[21:31], instr[20], instr[12:20], Repl(instr[31], 12)))
# Register addresses decoder
rs1Id = (instr[15:20])
rs2Id = (instr[20:25])
rdId = ( instr[7:12])
rdId = (instr[7:12])
# Function code decdore
funct3 = (instr[12:15])

8
10_lui_auipc/soc.py
View File

@@ -64,11 +64,9 @@ class SOC(Elaboratable):
# Immediate format decoder
Uimm = (Cat(Const(0, 12), instr[12:32]))
Iimm = (Cat(instr[20:31], Repl(instr[31], 21)))
Simm = (Cat(instr[7:12], Cat(instr[25:31], Repl(instr[31], 21)))),
Bimm = (Cat(0, Cat(instr[8:12], Cat(instr[25:31], Cat(
instr[7], Repl(instr[31], 20))))))
Jimm = (Cat(0, Cat(instr[21:31], Cat(instr[20], Cat(
instr[12:20], Repl(instr[31], 12))))))
Simm = (Cat(instr[7:12], instr[25:31], Repl(instr[31], 21))),
Bimm = (Cat(0, instr[8:12], instr[25:31], instr[7], Repl(instr[31], 20)))
Jimm = (Cat(0, instr[21:31], instr[20], instr[12:20], Repl(instr[31], 12)))
# Register addresses decoder
rs1Id = (instr[15:20])