Add boards directory with a generic top and platform specific modules.

01_blink/blink.py

@@ -1,38 +0,0 @@
-from amaranth import *
-from amaranth_boards.arty_a7 import *
-
-from soc import SOC
-
-# A platform contains board specific information about FPGA pin assignments,
-# toolchain and specific information for uploading the bitfile.
-platform = ArtyA7_35Platform(toolchain="Symbiflow")
-
-# We need a top level module
-m = Module()
-
-# This is the instance of our SOC
-soc = SOC()
-
-# The SOC is turned into a submodule (fragment) of our top level module.
-m.submodules.soc = soc
-
-# The platform allows access to the various resources defined by the board
-# definition from amaranth-boards.
-led0 = platform.request('led', 0)
-led1 = platform.request('led', 1)
-led2 = platform.request('led', 2)
-led3 = platform.request('led', 3)
-rgb = platform.request('rgb_led')
-
-# We connect the SOC leds signal to the various LEDs on the board.
-m.d.comb += [
-    led0.o.eq(soc.leds[0]),
-    led1.o.eq(soc.leds[1]),
-    led1.o.eq(soc.leds[2]),
-    led1.o.eq(soc.leds[3]),
-    rgb.r.o.eq(soc.leds[4]),
-]
-
-# To generate the bitstream, we build() the platform using our top level
-# module m.
-platform.build(m, do_program=False)

02_slower_blinky/blink.py

@@ -1,38 +0,0 @@
-from amaranth import *
-from amaranth_boards.arty_a7 import *
-
-from soc import SOC
-
-# A platform contains board specific information about FPGA pin assignments,
-# toolchain and specific information for uploading the bitfile.
-platform = ArtyA7_35Platform(toolchain="Symbiflow")
-
-# We need a top level module
-m = Module()
-
-# This is the instance of our SOC
-soc = SOC()
-
-# The SOC is turned into a submodule (fragment) of our top level module.
-m.submodules.soc = soc
-
-# The platform allows access to the various resources defined by the board
-# definition from amaranth-boards.
-led0 = platform.request('led', 0)
-led1 = platform.request('led', 1)
-led2 = platform.request('led', 2)
-led3 = platform.request('led', 3)
-rgb = platform.request('rgb_led')
-
-# We connect the SOC leds signal to the various LEDs on the board.
-m.d.comb += [
-    led0.o.eq(soc.leds[0]),
-    led1.o.eq(soc.leds[1]),
-    led1.o.eq(soc.leds[2]),
-    led1.o.eq(soc.leds[3]),
-    rgb.r.o.eq(soc.leds[4]),
-]
-
-# To generate the bitstream, we build() the platform using our top level
-# module m.
-platform.build(m, do_program=False)

boards/digilent_arty_a7.py

@@ -0,0 +1,18 @@
+from amaranth_boards.arty_a7 import *
+
+from top import Top
+
+if __name__ == "__main__":
+    platform = ArtyA7_35Platform(toolchain="Symbiflow")
+
+    # The platform allows access to the various resources defined by the board
+    # definition from amaranth-boards.
+    led0 = platform.request('led', 0)
+    led1 = platform.request('led', 1)
+    led2 = platform.request('led', 2)
+    led3 = platform.request('led', 3)
+    rgb = platform.request('rgb_led')
+    leds = [led0, led1, led2, led3, rgb.r]
+
+    platform.build(Top(leds), do_program=True)
+

boards/digilent_cmod_a7.py

@@ -0,0 +1,15 @@
+from amaranth_boards.cmod_a7 import *
+
+from top import Top
+
+if __name__ == "__main__":
+    platform = CmodA7_35Platform(toolchain="Symbiflow")
+
+    # The platform allows access to the various resources defined
+    # by the board definition from amaranth-boards.
+    led0 = platform.request('led', 0)
+    led1 = platform.request('led', 1)
+    rgb = platform.request('rgb_led')
+    leds = [led0, led1, rgb.r, rgb.g, rgb.b]
+
+    platform.build(Top(leds), do_program=True)

boards/top.py

@@ -0,0 +1,40 @@
+from amaranth import *
+
+import sys
+
+class Top(Elaboratable):
+    def __init__(self, leds):
+        if len(sys.argv) == 1:
+            print("Usage: {} step_number".format(sys.argv[0]))
+            exit(1)
+        step = int(sys.argv[1])
+        print("step = {}".format(step))
+        self.leds = leds
+
+        if step == 1:
+            path = "01_blink"
+        if step == 2:
+            path = "02_slower_blinky"
+        else:
+            print("Invalid step_number {}.".format(step))
+            exit(1)
+        sys.path.append(path)
+        from soc import SOC
+        self.soc = SOC()
+
+    def elaborate(self, platform):
+        m = Module()
+        soc = self.soc
+        leds = self.leds
+        m.submodules.soc = soc
+
+        # We connect the SOC leds signal to the various LEDs on the board.
+        m.d.comb += [
+            leds[0].o.eq(soc.leds[0]),
+            leds[1].o.eq(soc.leds[1]),
+            leds[2].o.eq(soc.leds[2]),
+            leds[3].o.eq(soc.leds[3]),
+            leds[4].o.eq(soc.leds[4]),
+        ]
+
+        return m