Add step 19 and run simulation in verilator.

19_verilator/run_verilator.sh

@@ -0,0 +1,27 @@
+#!/bin/bash
+
+set -e
+
+echo "Make sure:"
+echo "  - you've compiled a design previously, so build/top.v exists"
+echo "  - you've added the snippet.v to the 'top' module in build/top.v"
+echo ""
+read -n 1 -s -r -p "Press any key to continue or Ctrl-C to stop."
+
+cd 19_verilator/.. || cd ../19_verilator/..
+
+# generate C++ sources in 'obj_dir'
+verilator \
+	-DBENCH \
+	-DBOARD_FREQ=12 \
+	-Wno-fatal \
+	--top-module soc \
+	-cc -exe \
+	19_verilator/sim_main.cpp \
+	build/top.v
+
+# compile C++ sources
+make -C obj_dir -j8 -f Vsoc.mk
+
+# run the simulation
+./obj_dir/Vsoc

19_verilator/sim_main.cpp

@@ -0,0 +1,15 @@
+#include "Vsoc.h"
+#include "verilated.h"
+#include <iostream>
+
+int
+main(int argc, char **argv, char **env)
+{
+	Vsoc top;
+	top.clk = 0;
+	while (!Verilated::gotFinish()) {
+		top.clk = !top.clk;
+		top.eval();
+	}
+	return 0;
+}

19_verilator/snippet.v

@@ -0,0 +1,12 @@
+// add this to the end of the 'top' module in build/top.v
+
+  `ifdef BENCH
+  always @(posedge clk)
+  begin
+   	  if(uart_valid)
+	  begin
+		  $write("%c", memory_mem_wdata[7:0] );
+		  $fflush(32'h8000_0001);
+	  end
+  end
+  `endif