Add step10. LUI AUIPC.
This commit is contained in:
Bastian Löher
57
10_lui_auipc/bench.py
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57
10_lui_auipc/bench.py
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from amaranth import *
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from amaranth.sim import *
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from soc import SOC
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soc = SOC()
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sim = Simulator(soc)
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prev_clk = 0
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def proc():
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while True:
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global prev_clk
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clk = yield soc.slow_clk
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if prev_clk == 0 and prev_clk != clk:
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state = (yield soc.state)
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if state == 2:
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print("-- NEW CYCLE -----------------------")
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print(" F: LEDS = {:05b}".format((yield soc.leds)))
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print(" F: pc={}".format((yield soc.pc)))
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print(" F: instr={:#032b}".format((yield soc.instr)))
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if (yield soc.isALUreg):
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print(" ALUreg rd={} rs1={} rs2={} funct3={}".format(
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(yield soc.rdId), (yield soc.rs1Id), (yield soc.rs2Id),
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(yield soc.funct3)))
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if (yield soc.isALUimm):
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print(" ALUimm rd={} rs1={} imm={} funct3={}".format(
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(yield soc.rdId), (yield soc.rs1Id), (yield soc.Iimm),
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(yield soc.funct3)))
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if (yield soc.isBranch):
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print(" BRANCH rs1={} rs2={}".format(
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(yield soc.rs1Id), (yield soc.rs2Id)))
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if (yield soc.isLoad):
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print(" LOAD")
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if (yield soc.isStore):
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print(" STORE")
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if (yield soc.isSystem):
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print(" SYSTEM")
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break
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if state == 4:
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print(" R: LEDS = {:05b}".format((yield soc.leds)))
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print(" R: rs1={}".format((yield soc.rs1)))
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print(" R: rs2={}".format((yield soc.rs2)))
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if state == 1:
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print(" E: LEDS = {:05b}".format((yield soc.leds)))
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print(" E: Writeback x{} = {:032b}".format((yield soc.rdId),
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(yield soc.writeBackData)))
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yield
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prev_clk = clk
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sim.add_clock(1e-6)
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sim.add_sync_process(proc)
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with sim.write_vcd('bench.vcd', 'bench.gtkw', traces=soc.ports):
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# Let's run for a quite long time
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sim.run_until(2, )
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38
10_lui_auipc/blink.py
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38
10_lui_auipc/blink.py
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from amaranth import *
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from amaranth_boards.arty_a7 import *
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from soc import SOC
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# A platform contains board specific information about FPGA pin assignments,
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# toolchain and specific information for uploading the bitfile.
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platform = ArtyA7_35Platform(toolchain="Symbiflow")
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# We need a top level module
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m = Module()
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# This is the instance of our SOC
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soc = SOC()
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# The SOC is turned into a submodule (fragment) of our top level module.
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m.submodules.soc = soc
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# The platform allows access to the various resources defined by the board
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# definition from amaranth-boards.
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led0 = platform.request('led', 0)
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led1 = platform.request('led', 1)
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led2 = platform.request('led', 2)
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led3 = platform.request('led', 3)
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rgb = platform.request('rgb_led')
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# We connect the SOC leds signal to the various LEDs on the board.
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m.d.comb += [
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led0.o.eq(soc.leds[0]),
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led1.o.eq(soc.leds[1]),
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led1.o.eq(soc.leds[2]),
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led1.o.eq(soc.leds[3]),
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rgb.r.o.eq(soc.leds[4]),
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]
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# To generate the bitstream, we build() the platform using our top level
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# module m.
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platform.build(m, do_program=False)
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201
10_lui_auipc/soc.py
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201
10_lui_auipc/soc.py
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import sys
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from amaranth import *
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from clockworks import Clockworks
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from riscv_assembler import RiscvAssembler
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class SOC(Elaboratable):
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def __init__(self):
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self.leds = Signal(5)
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# Signals in this list can easily be plotted as vcd traces
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self.ports = []
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a = RiscvAssembler()
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a.read("""begin:
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LUI x1, 0b11111111111111111111111111111111
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ORI x1, x1, 0b11111111111111111111111111111111
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EBREAK
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""")
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a.assemble()
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self.sequence = a.mem
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print("memory = {}".format(self.sequence))
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def elaborate(self, platform):
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m = Module()
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cw = Clockworks(slow=21, sim_slow=10)
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m.submodules.cw = cw
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# Program counter
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pc = Signal(32)
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# Current instruction
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instr = Signal(32, reset=0b0110011)
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# Instruction memory initialised with above 'sequence'
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mem = Array([Signal(32, reset=x, name="mem") for x in self.sequence])
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# Register bank
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regs = Array([Signal(32, name="x"+str(x)) for x in range(32)])
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rs1 = Signal(32)
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rs2 = Signal(32)
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# ALU registers
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aluOut = Signal(32)
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takeBranch = Signal(32)
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# Opcode decoder
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isALUreg = (instr[0:7] == 0b0110011)
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isALUimm = (instr[0:7] == 0b0010011)
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isBranch = (instr[0:7] == 0b1100011)
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isJALR = (instr[0:7] == 0b1100111)
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isJAL = (instr[0:7] == 0b1101111)
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isAUIPC = (instr[0:7] == 0b0010111)
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isLUI = (instr[0:7] == 0b0110111)
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isLoad = (instr[0:7] == 0b0000011)
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isStore = (instr[0:7] == 0b0100011)
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isSystem = (instr[0:7] == 0b1110011)
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# Immediate format decoder
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Uimm = (Cat(Repl(0, 12), instr[12:32]))
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Iimm = (Cat(instr[20:31], Repl(instr[31], 21)))
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Simm = (Cat(instr[7:12], Cat(instr[25:31], Repl(instr[31], 21)))),
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Bimm = (Cat(0, Cat(instr[8:12], Cat(instr[25:31], Cat(
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instr[7], Repl(instr[31], 20))))))
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Jimm = (Cat(0, Cat(instr[21:31], Cat(instr[20], Cat(
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instr[12:20], Repl(instr[31], 12))))))
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# Register addresses decoder
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rs1Id = (instr[15:20])
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rs2Id = (instr[20:25])
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rdId = ( instr[7:12])
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# Function code decdore
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funct3 = (instr[12:15])
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funct7 = (instr[25:32])
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# ALU
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aluIn1 = rs1
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aluIn2 = Mux(isALUreg, rs2, Iimm)
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shamt = Mux(isALUreg, rs2[0:5], instr[20:25])
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with m.Switch(funct3) as alu:
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with m.Case(0b000):
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m.d.comb += aluOut.eq(Mux(funct7[5] & instr[5],
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(aluIn1 - aluIn2), (aluIn1 + aluIn2)))
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with m.Case(0b001):
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m.d.comb += aluOut.eq(aluIn1 << shamt)
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with m.Case(0b010):
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m.d.comb += aluOut.eq(aluIn1.as_signed() < aluIn2.as_signed())
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with m.Case(0b011):
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m.d.comb += aluOut.eq(aluIn1 < aluIn2)
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with m.Case(0b100):
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m.d.comb += aluOut.eq(aluIn1 ^ aluIn2)
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with m.Case(0b101):
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m.d.comb += aluOut.eq(Mux(
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funct7[5],
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(aluIn1.as_signed() >> shamt), # arithmetic right shift
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(aluIn1.as_unsigned() >> shamt))) # logical right shift
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with m.Case(0b110):
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m.d.comb += aluOut.eq(aluIn1 | aluIn2)
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with m.Case(0b111):
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m.d.comb += aluOut.eq(aluIn1 & aluIn2)
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with m.Switch(funct3) as alu_branch:
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with m.Case(0b000):
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m.d.comb += takeBranch.eq(rs1 == rs2)
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with m.Case(0b001):
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m.d.comb += takeBranch.eq(rs1 != rs2)
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with m.Case(0b100):
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m.d.comb += takeBranch.eq(rs1.as_signed() < rs2.as_signed())
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with m.Case(0b101):
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m.d.comb += takeBranch.eq(rs1.as_signed() >= rs2.as_signed())
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with m.Case(0b110):
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m.d.comb += takeBranch.eq(rs1 < rs2)
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with m.Case(0b111):
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m.d.comb += takeBranch.eq(rs1 >= rs2)
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with m.Case("---"):
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m.d.comb += takeBranch.eq(0)
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# Next program counter is either next intstruction or depends on
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# jump target
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nextPc = Mux((isBranch & takeBranch), pc + Bimm,
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Mux(isJAL, pc + Jimm,
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Mux(isJALR, rs1 + Iimm,
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pc + 4)))
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# Main state machine
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with m.FSM(reset="FETCH_INSTR", domain="slow") as fsm:
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with m.State("FETCH_INSTR"):
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m.d.slow += instr.eq(mem[pc[2:32]])
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m.next = "FETCH_REGS"
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with m.State("FETCH_REGS"):
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m.d.slow += [
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rs1.eq(regs[rs1Id]),
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rs2.eq(regs[rs2Id])
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]
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m.next = "EXECUTE"
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with m.State("EXECUTE"):
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m.d.slow += pc.eq(nextPc)
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m.next = "FETCH_INSTR"
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# Register write back
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writeBackData = Mux((isJAL | isJALR), (pc + 4),
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Mux(isLUI, Uimm,
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Mux(isAUIPC, (pc + Uimm), aluOut)))
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writeBackEn = fsm.ongoing("EXECUTE") & (
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isALUreg |
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isALUimm |
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isLUI |
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isAUIPC |
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isJAL |
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isJALR)
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with m.If(writeBackEn & (rdId != 0)):
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m.d.slow += regs[rdId].eq(writeBackData)
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# Assign writeBackData to leds to see what is happening
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m.d.slow += self.leds.eq(writeBackData)
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# Export signals for simulation
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def export(signal, name):
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if type(signal) is not Signal:
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newsig = Signal(signal.shape(), name = name)
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m.d.comb += newsig.eq(signal)
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else:
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newsig = signal
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self.ports.append(newsig)
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setattr(self, name, newsig)
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if platform is None:
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export(ClockSignal("slow"), "slow_clk")
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export(pc, "pc")
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export(instr, "instr")
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export(isALUreg, "isALUreg")
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export(isALUimm, "isALUimm")
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export(isBranch, "isBranch")
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export(isJAL, "isJAL")
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export(isJALR, "isJALR")
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export(isLoad, "isLoad")
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export(isStore, "isStore")
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export(isSystem, "isSystem")
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export(rdId, "rdId")
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export(rs1Id, "rs1Id")
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export(rs2Id, "rs2Id")
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export(Iimm, "Iimm")
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export(Bimm, "Bimm")
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export(Jimm, "Jimm")
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export(funct3, "funct3")
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export(rdId, "rdId")
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export(rs1, "rs1")
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export(rs2, "rs2")
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export(writeBackData, "writeBackData")
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export(writeBackEn, "writeBackEn")
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export(aluOut, "aluOut")
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export((1 << fsm.state), "state")
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return m
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