39 lines
1.1 KiB
Python
39 lines
1.1 KiB
Python
from amaranth import *
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from amaranth_boards.arty_a7 import *
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from soc import SOC
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# A platform contains board specific information about FPGA pin assignments,
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# toolchain and specific information for uploading the bitfile.
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platform = ArtyA7_35Platform(toolchain="Symbiflow")
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# We need a top level module
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m = Module()
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# This is the instance of our SOC
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soc = SOC()
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# The SOC is turned into a submodule (fragment) of our top level module.
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m.submodules.soc = soc
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# The platform allows access to the various resources defined by the board
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# definition from amaranth-boards.
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led0 = platform.request('led', 0)
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led1 = platform.request('led', 1)
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led2 = platform.request('led', 2)
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led3 = platform.request('led', 3)
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rgb = platform.request('rgb_led')
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# We connect the SOC leds signal to the various LEDs on the board.
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m.d.comb += [
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led0.o.eq(soc.leds[0]),
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led1.o.eq(soc.leds[1]),
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led1.o.eq(soc.leds[2]),
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led1.o.eq(soc.leds[3]),
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rgb.r.o.eq(soc.leds[4]),
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]
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# To generate the bitstream, we build() the platform using our top level
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# module m.
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platform.build(m, do_program=False)
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