83 lines
		
	
	
		
			2.3 KiB
		
	
	
	
		
			Python
		
	
	
	
	
	
			
		
		
	
	
			83 lines
		
	
	
		
			2.3 KiB
		
	
	
	
		
			Python
		
	
	
	
	
	
| import sys
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| from amaranth import *
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| 
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| from clockworks import Clockworks
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| from memory import Memory
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| from cpu import CPU
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| 
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| class SOC(Elaboratable):
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| 
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|     def __init__(self):
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| 
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|         self.leds = Signal(5)
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| 
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|         # Signals in this list can easily be plotted as vcd traces
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|         self.ports = []
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| 
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|     def elaborate(self, platform):
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| 
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|         m = Module()
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|         cw = Clockworks()
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|         memory = DomainRenamer("slow")(Memory())
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|         cpu = DomainRenamer("slow")(CPU())
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|         m.submodules.cw = cw
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|         m.submodules.cpu = cpu
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|         m.submodules.memory = memory
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| 
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|         self.cpu = cpu
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|         self.memory = memory
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| 
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|         x10 = Signal(32)
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| 
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|         # Connect memory to CPU
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|         m.d.comb += [
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|             memory.mem_addr.eq(cpu.mem_addr),
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|             memory.mem_rstrb.eq(cpu.mem_rstrb),
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|             cpu.mem_rdata.eq(memory.mem_rdata)
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|         ]
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| 
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|         # CPU debug output
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|         m.d.comb += [
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|             x10.eq(cpu.x10),
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|             self.leds.eq(x10[0:5])
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|         ]
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| 
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|         # Export signals for simulation
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|         def export(signal, name):
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|             if type(signal) is not Signal:
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|                 newsig = Signal(signal.shape(), name = name)
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|                 m.d.comb += newsig.eq(signal)
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|             else:
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|                 newsig = signal
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|             self.ports.append(newsig)
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|             setattr(self, name, newsig)
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| 
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|         if platform is None:
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|             export(ClockSignal("slow"), "slow_clk")
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|             #export(pc, "pc")
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|             #export(instr, "instr")
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|             #export(isALUreg, "isALUreg")
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|             #export(isALUimm, "isALUimm")
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|             #export(isBranch, "isBranch")
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|             #export(isJAL, "isJAL")
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|             #export(isJALR, "isJALR")
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|             #export(isLoad, "isLoad")
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|             #export(isStore, "isStore")
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|             #export(isSystem, "isSystem")
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|             #export(rdId, "rdId")
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|             #export(rs1Id, "rs1Id")
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|             #export(rs2Id, "rs2Id")
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|             #export(Iimm, "Iimm")
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|             #export(Bimm, "Bimm")
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|             #export(Jimm, "Jimm")
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|             #export(funct3, "funct3")
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|             #export(rdId, "rdId")
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|             #export(rs1, "rs1")
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|             #export(rs2, "rs2")
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|             #export(writeBackData, "writeBackData")
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|             #export(writeBackEn, "writeBackEn")
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|             #export(aluOut, "aluOut")
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|             #export((1 << cpu.fsm.state), "state")
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| 
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|         return m
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