Add step 15: load.
This commit is contained in:
Bastian Löher
61
15_load/bench.py
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61
15_load/bench.py
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@@ -0,0 +1,61 @@
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from amaranth import *
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from amaranth.sim import *
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from soc import SOC
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soc = SOC()
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sim = Simulator(soc)
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prev_clk = 0
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def proc():
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cpu = soc.cpu
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mem = soc.memory
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while True:
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global prev_clk
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clk = yield soc.slow_clk
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if prev_clk == 0 and prev_clk != clk:
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state = (yield soc.cpu.fsm.state)
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if state == 2:
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print("-- NEW CYCLE -----------------------")
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print(" F: LEDS = {:05b}".format((yield soc.leds)))
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print(" F: pc={}".format((yield cpu.pc)))
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print(" F: instr={:#032b}".format((yield cpu.instr)))
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if (yield cpu.isALUreg):
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print(" ALUreg rd={} rs1={} rs2={} funct3={}".format(
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(yield cpu.rdId), (yield cpu.rs1Id), (yield cpu.rs2Id),
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(yield cpu.funct3)))
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if (yield cpu.isALUimm):
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print(" ALUimm rd={} rs1={} imm={} funct3={}".format(
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(yield cpu.rdId), (yield cpu.rs1Id), (yield cpu.Iimm),
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(yield cpu.funct3)))
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if (yield cpu.isBranch):
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print(" BRANCH rs1={} rs2={}".format(
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(yield cpu.rs1Id), (yield cpu.rs2Id)))
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if (yield cpu.isLoad):
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print(" LOAD")
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if (yield cpu.isStore):
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print(" STORE")
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if (yield cpu.isSystem):
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print(" SYSTEM")
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break
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if state == 4:
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print(" R: LEDS = {:05b}".format((yield soc.leds)))
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print(" R: rs1={}".format((yield cpu.rs1)))
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print(" R: rs2={}".format((yield cpu.rs2)))
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if state == 1:
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print(" E: LEDS = {:05b}".format((yield soc.leds)))
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print(" E: Writeback x{} = {:032b}".format((yield cpu.rdId),
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(yield cpu.writeBackData)))
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if state == 8:
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print(" NEW")
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yield
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prev_clk = clk
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sim.add_clock(1e-6)
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sim.add_sync_process(proc)
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with sim.write_vcd('bench.vcd', 'bench.gtkw', traces=soc.ports):
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# Let's run for a quite long time
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sim.run_until(2, )
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38
15_load/blink.py
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38
15_load/blink.py
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@@ -0,0 +1,38 @@
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from amaranth import *
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from amaranth_boards.arty_a7 import *
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from soc import SOC
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# A platform contains board specific information about FPGA pin assignments,
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# toolchain and specific information for uploading the bitfile.
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platform = ArtyA7_35Platform(toolchain="Symbiflow")
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# We need a top level module
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m = Module()
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# This is the instance of our SOC
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soc = SOC()
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# The SOC is turned into a submodule (fragment) of our top level module.
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m.submodules.soc = soc
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# The platform allows access to the various resources defined by the board
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# definition from amaranth-boards.
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led0 = platform.request('led', 0)
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led1 = platform.request('led', 1)
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led2 = platform.request('led', 2)
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led3 = platform.request('led', 3)
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rgb = platform.request('rgb_led')
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# We connect the SOC leds signal to the various LEDs on the board.
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m.d.comb += [
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led0.o.eq(soc.leds[0]),
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led1.o.eq(soc.leds[1]),
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led1.o.eq(soc.leds[2]),
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led1.o.eq(soc.leds[3]),
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rgb.r.o.eq(soc.leds[4]),
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]
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# To generate the bitstream, we build() the platform using our top level
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# module m.
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platform.build(m, do_program=False)
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254
15_load/cpu.py
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254
15_load/cpu.py
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@@ -0,0 +1,254 @@
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from amaranth import *
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class CPU(Elaboratable):
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def __init__(self):
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self.mem_addr = Signal(32)
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self.mem_rstrb = Signal()
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self.mem_rdata = Signal(32)
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self.x10 = Signal(32)
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self.fsm = None
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def elaborate(self, platform):
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m = Module()
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# Program counter
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pc = Signal(32)
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self.pc = pc
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# Memory
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mem_rdata = self.mem_rdata
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# Current instruction
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instr = Signal(32, reset=0b0110011)
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self.instr = instr
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# Register bank
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regs = Array([Signal(32, name="x"+str(x)) for x in range(32)])
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rs1 = Signal(32)
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rs2 = Signal(32)
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# ALU registers
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aluOut = Signal(32)
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takeBranch = Signal(32)
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# Opcode decoder
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# It is nice to have these as actual signals for simulation
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isALUreg = Signal()
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isALUimm = Signal()
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isBranch = Signal()
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isJALR = Signal()
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isJAL = Signal()
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isAUIPC = Signal()
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isLUI = Signal()
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isLoad = Signal()
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isStore = Signal()
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isSystem = Signal()
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m.d.comb += [
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isALUreg.eq(instr[0:7] == 0b0110011),
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isALUimm.eq(instr[0:7] == 0b0010011),
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isBranch.eq(instr[0:7] == 0b1100011),
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isJALR.eq(instr[0:7] == 0b1100111),
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isJAL.eq(instr[0:7] == 0b1101111),
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isAUIPC.eq(instr[0:7] == 0b0010111),
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isLUI.eq(instr[0:7] == 0b0110111),
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isLoad.eq(instr[0:7] == 0b0000011),
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isStore.eq(instr[0:7] == 0b0100011),
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isSystem.eq(instr[0:7] == 0b1110011)
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]
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self.isALUreg = isALUreg
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self.isALUimm = isALUimm
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self.isBranch = isBranch
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self.isLoad = isLoad
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self.isStore = isStore
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self.isSystem = isSystem
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# Extend a signal with a sign bit repeated n times
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def SignExtend(signal, sign, n):
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return Cat(signal, Repl(sign, n))
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# Immediate format decoder
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Uimm = Cat(Repl(0, 12), instr[12:32])
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Iimm = Cat(instr[20:31], Repl(instr[31], 21))
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Simm = Cat(instr[7:12], instr[25:31], Repl(instr[31], 21))
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Bimm = Cat(0, instr[8:12], instr[25:31], instr[7],
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Repl(instr[31], 20))
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Jimm = Cat(0, instr[21:31], instr[20], instr[12:20],
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Repl(instr[31], 12))
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self.Iimm = Iimm
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# Register addresses decoder
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rs1Id = instr[15:20]
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rs2Id = instr[20:25]
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rdId = instr[7:12]
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self.rdId = rdId
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self.rs1Id = rs1Id
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self.rs2Id = rs2Id
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# Function code decdore
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funct3 = instr[12:15]
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funct7 = instr[25:32]
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self.funct3 = funct3
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# ALU
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aluIn1 = Signal.like(rs1)
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aluIn2 = Signal.like(rs2)
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shamt = Signal(5)
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aluMinus = Signal(33)
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aluPlus = Signal.like(aluIn1)
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m.d.comb += [
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aluIn1.eq(rs1),
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aluIn2.eq(Mux((isALUreg | isBranch), rs2, Iimm)),
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shamt.eq(Mux(isALUreg, rs2[0:5], instr[20:25]))
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]
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m.d.comb += [
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aluMinus.eq(Cat(~aluIn1, C(0,1)) + Cat(aluIn2, C(0,1)) + 1),
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aluPlus.eq(aluIn1 + aluIn2)
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]
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EQ = aluMinus[0:32] == 0
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LTU = aluMinus[32]
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LT = Mux((aluIn1[31] ^ aluIn2[31]), aluIn1[31], aluMinus[32])
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def flip32(x):
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a = [x[i] for i in range(0, 32)]
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return Cat(*reversed(a))
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# TODO: check these again!
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shifter_in = Mux(funct3 == 0b001, flip32(aluIn1), aluIn1)
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shifter = Cat(shifter_in, (instr[30] & aluIn1[31])) >> aluIn2[0:5]
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leftshift = flip32(shifter)
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with m.Switch(funct3) as alu:
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with m.Case(0b000):
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m.d.comb += aluOut.eq(Mux(funct7[5] & instr[5],
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aluMinus[0:32], aluPlus))
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with m.Case(0b001):
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m.d.comb += aluOut.eq(leftshift)
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with m.Case(0b010):
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m.d.comb += aluOut.eq(LT)
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with m.Case(0b011):
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m.d.comb += aluOut.eq(LTU)
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with m.Case(0b100):
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m.d.comb += aluOut.eq(aluIn1 ^ aluIn2)
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with m.Case(0b101):
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m.d.comb += aluOut.eq(shifter)
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with m.Case(0b110):
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m.d.comb += aluOut.eq(aluIn1 | aluIn2)
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with m.Case(0b111):
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m.d.comb += aluOut.eq(aluIn1 & aluIn2)
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with m.Switch(funct3) as alu_branch:
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with m.Case(0b000):
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m.d.comb += takeBranch.eq(EQ)
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with m.Case(0b001):
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m.d.comb += takeBranch.eq(~EQ)
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with m.Case(0b100):
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m.d.comb += takeBranch.eq(LT)
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with m.Case(0b101):
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m.d.comb += takeBranch.eq(~LT)
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with m.Case(0b110):
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m.d.comb += takeBranch.eq(LTU)
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with m.Case(0b111):
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m.d.comb += takeBranch.eq(~LTU)
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with m.Case("---"):
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m.d.comb += takeBranch.eq(0)
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# Next program counter is either next intstruction or depends on
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# jump target
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pcPlusImm = pc + Mux(instr[3], Jimm[0:32],
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Mux(instr[4], Uimm[0:32],
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Bimm[0:32]))
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pcPlus4 = pc + 4
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nextPc = Mux(((isBranch & takeBranch) | isJAL), pcPlusImm,
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Mux(isJALR, Cat(C(0, 1), aluPlus[1:32]),
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pcPlus4))
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# Main state machine
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with m.FSM(reset="FETCH_INSTR") as fsm:
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self.fsm = fsm
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with m.State("FETCH_INSTR"):
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m.next = "WAIT_INSTR"
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with m.State("WAIT_INSTR"):
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m.d.sync += instr.eq(self.mem_rdata)
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m.next = ("FETCH_REGS")
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with m.State("FETCH_REGS"):
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m.d.sync += [
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rs1.eq(regs[rs1Id]),
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rs2.eq(regs[rs2Id])
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]
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m.next = "EXECUTE"
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with m.State("EXECUTE"):
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with m.If(~isSystem):
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m.d.sync += pc.eq(nextPc)
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with m.If(isLoad):
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m.next = "LOAD"
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with m.Else():
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m.next = "FETCH_INSTR"
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with m.State("LOAD"):
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m.next = "WAIT_DATA"
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with m.State("WAIT_DATA"):
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m.next = "FETCH_INSTR"
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## Load and store
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loadStoreAddr = Signal(32)
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m.d.comb += loadStoreAddr.eq(rs1 + Iimm)
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# Load
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memByteAccess = Signal()
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memHalfwordAccess = Signal()
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loadHalfword = Signal(16)
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loadByte = Signal(8)
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loadSign = Signal()
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loadData = Signal(32)
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m.d.comb += [
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memByteAccess.eq(funct3[0:2] == C(0,2)),
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memHalfwordAccess.eq(funct3[0:2] == C(1,2)),
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loadHalfword.eq(Mux(loadStoreAddr[1], mem_rdata[16:32],
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mem_rdata[0:16])),
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loadByte.eq(Mux(loadStoreAddr[0], loadHalfword[8:16],
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loadHalfword[0:8])),
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loadSign.eq(~funct3[2] & Mux(memByteAccess, loadByte[7],
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loadHalfword[15])),
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loadData.eq(
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Mux(memByteAccess, SignExtend(loadByte, loadSign, 24),
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Mux(memHalfwordAccess, SignExtend(loadHalfword,
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loadSign, 16),
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mem_rdata)))
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]
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# Wire memory address to pc or loadStoreAddr
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m.d.comb += [
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self.mem_addr.eq(
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Mux(fsm.ongoing("WAIT_INSTR") | fsm.ongoing("FETCH_INSTR"),
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pc, loadStoreAddr)),
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self.mem_rstrb.eq(fsm.ongoing("FETCH_INSTR") | fsm.ongoing("LOAD"))
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]
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# Register write back
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writeBackData = Mux((isJAL | isJALR), pcPlus4,
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Mux(isLUI, Uimm,
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Mux(isAUIPC, pcPlusImm,
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Mux(isLoad, loadData,
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aluOut))))
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writeBackEn = ((fsm.ongoing("EXECUTE") & ~isBranch & ~isStore & ~isLoad)
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| fsm.ongoing("WAIT_DATA"))
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self.writeBackData = writeBackData
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with m.If(writeBackEn & (rdId != 0)):
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m.d.sync += regs[rdId].eq(writeBackData)
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# Also assign to debug output to see what is happening
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with m.If(rdId == 10):
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m.d.sync += self.x10.eq(writeBackData)
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return m
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58
15_load/memory.py
Normal file
58
15_load/memory.py
Normal file
@@ -0,0 +1,58 @@
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from amaranth import *
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from riscv_assembler import RiscvAssembler
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class Memory(Elaboratable):
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def __init__(self):
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a = RiscvAssembler()
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a.read("""begin:
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LI s0, 0
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LI s1, 16
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l0:
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LB a0, s0, 400
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CALL wait
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ADDI s0, s0, 1
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BNE s0, s1, l0
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EBREAK
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wait:
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LI t0, 1
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SLLI t0, t0, 20
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l1:
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ADDI t0, t0, -1
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BNEZ t0, l1
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RET
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""")
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a.assemble()
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self.instructions = a.mem
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print("memory = {}".format(self.instructions))
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# Instruction memory initialised with above instructions
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self.mem = Array([Signal(32, reset=x, name="mem{}".format(i))
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for i,x in enumerate(self.instructions)])
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self.mem_addr = Signal(32)
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self.mem_rdata = Signal(32)
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self.mem_rstrb = Signal()
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while(len(self.mem) < 100):
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self.mem.append(0)
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self.mem.append(0x04030201)
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self.mem.append(0x08070605)
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self.mem.append(0x0c0b0a09)
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self.mem.append(0xff0f0e0d)
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print(self.mem)
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def elaborate(self, platform):
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m = Module()
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with m.If(self.mem_rstrb):
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m.d.sync += self.mem_rdata.eq(self.mem[self.mem_addr[2:32]])
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return m
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82
15_load/soc.py
Normal file
82
15_load/soc.py
Normal file
@@ -0,0 +1,82 @@
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import sys
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from amaranth import *
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from clockworks import Clockworks
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from memory import Memory
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from cpu import CPU
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class SOC(Elaboratable):
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def __init__(self):
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self.leds = Signal(5)
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# Signals in this list can easily be plotted as vcd traces
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self.ports = []
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def elaborate(self, platform):
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m = Module()
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cw = Clockworks()
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memory = DomainRenamer("slow")(Memory())
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cpu = DomainRenamer("slow")(CPU())
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m.submodules.cw = cw
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m.submodules.cpu = cpu
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m.submodules.memory = memory
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self.cpu = cpu
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self.memory = memory
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x10 = Signal(32)
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# Connect memory to CPU
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m.d.comb += [
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memory.mem_addr.eq(cpu.mem_addr),
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memory.mem_rstrb.eq(cpu.mem_rstrb),
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cpu.mem_rdata.eq(memory.mem_rdata)
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]
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# CPU debug output
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m.d.comb += [
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x10.eq(cpu.x10),
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self.leds.eq(x10[0:5])
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]
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# Export signals for simulation
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||||
def export(signal, name):
|
||||
if type(signal) is not Signal:
|
||||
newsig = Signal(signal.shape(), name = name)
|
||||
m.d.comb += newsig.eq(signal)
|
||||
else:
|
||||
newsig = signal
|
||||
self.ports.append(newsig)
|
||||
setattr(self, name, newsig)
|
||||
|
||||
if platform is None:
|
||||
export(ClockSignal("slow"), "slow_clk")
|
||||
#export(pc, "pc")
|
||||
#export(instr, "instr")
|
||||
#export(isALUreg, "isALUreg")
|
||||
#export(isALUimm, "isALUimm")
|
||||
#export(isBranch, "isBranch")
|
||||
#export(isJAL, "isJAL")
|
||||
#export(isJALR, "isJALR")
|
||||
#export(isLoad, "isLoad")
|
||||
#export(isStore, "isStore")
|
||||
#export(isSystem, "isSystem")
|
||||
#export(rdId, "rdId")
|
||||
#export(rs1Id, "rs1Id")
|
||||
#export(rs2Id, "rs2Id")
|
||||
#export(Iimm, "Iimm")
|
||||
#export(Bimm, "Bimm")
|
||||
#export(Jimm, "Jimm")
|
||||
#export(funct3, "funct3")
|
||||
#export(rdId, "rdId")
|
||||
#export(rs1, "rs1")
|
||||
#export(rs2, "rs2")
|
||||
#export(writeBackData, "writeBackData")
|
||||
#export(writeBackEn, "writeBackEn")
|
||||
#export(aluOut, "aluOut")
|
||||
#export((1 << cpu.fsm.state), "state")
|
||||
|
||||
return m
|
||||
@@ -40,6 +40,8 @@ class Top(Elaboratable):
|
||||
path = "13_subroutines"
|
||||
elif step == 14:
|
||||
path = "14_subroutines_v2"
|
||||
elif step == 15:
|
||||
path = "15_load"
|
||||
else:
|
||||
print("Invalid step_number {}.".format(step))
|
||||
exit(1)
|
||||
|
||||
Reference in New Issue
Block a user