Up to date instructions to install nextpnr-xilinx
Simple example using it
This commit is contained in:
51
Basic/ARTY/ARTY_blink/arty.xdc
Normal file
51
Basic/ARTY/ARTY_blink/arty.xdc
Normal file
@@ -0,0 +1,51 @@
|
||||
# R
|
||||
set_property LOC G6 [get_ports led[0]]
|
||||
set_property LOC G3 [get_ports led[1]]
|
||||
set_property LOC J3 [get_ports led[2]]
|
||||
set_property LOC K1 [get_ports led[3]]
|
||||
# G
|
||||
set_property LOC F6 [get_ports led[4]]
|
||||
set_property LOC J4 [get_ports led[5]]
|
||||
set_property LOC J2 [get_ports led[6]]
|
||||
set_property LOC H6 [get_ports led[7]]
|
||||
# B
|
||||
set_property LOC E1 [get_ports led[8]]
|
||||
set_property LOC G4 [get_ports led[9]]
|
||||
set_property LOC H4 [get_ports led[10]]
|
||||
set_property LOC K2 [get_ports led[11]]
|
||||
|
||||
# second row
|
||||
# set_property LOC H5 [get_ports led[12]]
|
||||
# set_property LOC J5 [get_ports led[13]]
|
||||
# set_property LOC T9 [get_ports led[14]]
|
||||
# set_property LOC T10 [get_ports led[15]]
|
||||
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports led[0]]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports led[1]]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports led[2]]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports led[3]]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports led[4]]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports led[5]]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports led[6]]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports led[7]]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports led[8]]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports led[9]]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports led[10]]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports led[11]]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports led[12]]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports led[13]]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports led[14]]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports led[15]]
|
||||
|
||||
set_property LOC A8 [get_ports sw[0]]
|
||||
set_property LOC C11 [get_ports sw[1]]
|
||||
set_property LOC C10 [get_ports sw[2]]
|
||||
set_property LOC A10 [get_ports sw[3]]
|
||||
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports sw[0]]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports sw[1]]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports sw[2]]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports sw[3]]
|
||||
|
||||
set_property LOC E3 [get_ports clk_i]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports clk_i]
|
||||
32
Basic/ARTY/ARTY_blink/blinky.v
Normal file
32
Basic/ARTY/ARTY_blink/blinky.v
Normal file
@@ -0,0 +1,32 @@
|
||||
module top (input clk_i, input [3:0] sw, output [11:0] led);
|
||||
|
||||
//assign led = {&sw, |sw, ^sw, ~^sw};
|
||||
|
||||
wire clk;
|
||||
BUFGCTRL bufg_i (
|
||||
.I0(clk_i),
|
||||
.CE0(1'b1),
|
||||
.S0(1'b1),
|
||||
.O(clk)
|
||||
);
|
||||
|
||||
|
||||
// wire clk = clk_i;
|
||||
|
||||
reg clkdiv;
|
||||
reg [22:0] ctr;
|
||||
|
||||
always @(posedge clk) {clkdiv, ctr} <= ctr + 1'b1;
|
||||
|
||||
reg [5:0] led_r = 4'b0000;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (clkdiv)
|
||||
led_r <= led_r + 1'b1;
|
||||
end
|
||||
|
||||
wire [11:0] led_s = led_r[3:0] << (4 * led_r[5:4]);
|
||||
|
||||
assign led = &(led_r[5:4]) ? {3{led_r[3:0]}} : led_s;
|
||||
|
||||
endmodule
|
||||
15
Basic/ARTY/ARTY_blink/makeit.sh
Executable file
15
Basic/ARTY/ARTY_blink/makeit.sh
Executable file
@@ -0,0 +1,15 @@
|
||||
#!/usr/bin/env bash
|
||||
PROJECT_NAME=blinky
|
||||
DB_DIR=/usr/share/nextpnr/prjxray-db
|
||||
CHIPDB_DIR=/usr/share/nextpnr/xilinx-chipdb
|
||||
PART=xc7a35tcsg324-1
|
||||
|
||||
set -ex
|
||||
yosys -p "synth_xilinx -flatten -abc9 -nobram -arch xc7 -top top; write_json ${PROJECT_NAME}.json" ${PROJECT_NAME}.v
|
||||
nextpnr-xilinx --chipdb ${CHIPDB_DIR}/xc7a35t.bin --xdc arty.xdc --json ${PROJECT_NAME}.json --write ${PROJECT_NAME}_routed.json --fasm ${PROJECT_NAME}.fasm
|
||||
fasm2frames --part ${PART} --db-root ${DB_DIR}/artix7 ${PROJECT_NAME}.fasm > ${PROJECT_NAME}.frames
|
||||
xc7frames2bit --part_file ${DB_DIR}/artix7/${PART}/part.yaml --part_name ${PART} --frm_file ${PROJECT_NAME}.frames --output_file ${PROJECT_NAME}.bit
|
||||
#To send to SRAM:
|
||||
openFPGALoader --board arty ${PROJECT_NAME}.bit
|
||||
#To send to FLASH:
|
||||
#openFPGALoader --board arty -f ${PROJECT_NAME}.bit
|
||||
@@ -34,3 +34,17 @@ set_property IOSTANDARD LVCMOS33 [get_ports RXD]
|
||||
# reset button
|
||||
set_property LOC C2 [get_ports RESET]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports RESET]
|
||||
|
||||
# SPI flash
|
||||
set_property LOC L13 [get_ports spi_cs_n]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports spi_cs_n]
|
||||
set_property LOC K17 [get_ports spi_mosi]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports spi_mosi]
|
||||
set_property LOC K18 [get_ports spi_miso]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports spi_miso]
|
||||
set_property LOC L16 [get_ports spi_clk]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports spi_clk]
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
@@ -47,11 +47,15 @@ union {
|
||||
uint8_t spi_bytes[4];
|
||||
} spi_u;
|
||||
|
||||
|
||||
#define ADDR_OFFSET 1024*1024
|
||||
// #define ADDR_OFFSET 3000000
|
||||
|
||||
/*
|
||||
* Restarts reading from the beginning of the stream.
|
||||
*/
|
||||
void spi_reset() {
|
||||
spi_addr = 1024*1024;
|
||||
spi_addr = ADDR_OFFSET;
|
||||
spi_word_addr = (uint32_t)(-1);
|
||||
}
|
||||
|
||||
@@ -171,8 +175,10 @@ int read_frame() {
|
||||
}
|
||||
if(poly_desc == 0xfe) {
|
||||
// Go to next 64kb block
|
||||
spi_addr -= ADDR_OFFSET;
|
||||
spi_addr &= ~65535;
|
||||
spi_addr += 65536;
|
||||
spi_addr += ADDR_OFFSET;
|
||||
return 1;
|
||||
}
|
||||
if(poly_desc == 0xfd) {
|
||||
|
||||
@@ -33,7 +33,7 @@ int main() {
|
||||
// Test whether mapped memory space is activated
|
||||
int has_SPI = FEMTOSOC_HAS_DEVICE(IO_MAPPED_SPI_FLASH_bit);
|
||||
|
||||
int addr = 0; // 1024*1024;
|
||||
int addr = 4000000; // 0; // 1024*1024;
|
||||
int data;
|
||||
GL_tty_init(); // uncomment if using OLED display instead of tty output.
|
||||
|
||||
|
||||
@@ -6,7 +6,7 @@
|
||||
`define NRV_IO_UART // Mapped IO, virtual UART (USB)
|
||||
`define NRV_IO_SSD1351 // Mapped IO, 128x128x64K OLED screen
|
||||
`define NRV_IO_MAX7219 // Mapped IO, 8x8 led matrix
|
||||
//`define NRV_MAPPED_SPI_FLASH // SPI flash mapped in address space.
|
||||
`define NRV_MAPPED_SPI_FLASH // SPI flash mapped in address space.
|
||||
|
||||
/************************* Processor configuration *******************************************************************/
|
||||
|
||||
|
||||
@@ -56,6 +56,11 @@
|
||||
`define SPI_FLASH_CONFIGURED
|
||||
`endif
|
||||
|
||||
`ifdef ARTY
|
||||
`define SPI_FLASH_READ
|
||||
`define SPI_FLASH_CONFIGURED
|
||||
`endif
|
||||
|
||||
`ifndef SPI_FLASH_DUMMY_CLOCKS
|
||||
`define SPI_FLASH_DUMMY_CLOCKS 8
|
||||
`endif
|
||||
|
||||
@@ -252,12 +252,12 @@ To see the list of supported boards:
|
||||
```
|
||||
$ openFLGALoader --list-boards
|
||||
```
|
||||
To flash to SRAM
|
||||
To send bitstream to SRAM (program temporarily)
|
||||
```
|
||||
$ openFLGALoader --board my_board my_design.bit
|
||||
```
|
||||
|
||||
To flash to FLASH
|
||||
To send bitstream to FLASH (program permanently)
|
||||
```
|
||||
$ openFLGALoader --board my_board -f my_design.bit
|
||||
```
|
||||
|
||||
@@ -1,8 +1,16 @@
|
||||
Installing open-source tools for ARTIX-7 FPGAs
|
||||
==============================================
|
||||
|
||||
There are two possible toolchains for ARTIX-7, either symbiflow
|
||||
(all-in-one, integrated, easier to install) or yosys + xray + nextpnr-xilinx
|
||||
(more complicated to install, but more up to date, and uses nextpnr
|
||||
instead of the heavier vpr).
|
||||
|
||||
SYMBIFLOW
|
||||
=========
|
||||
|
||||
Step 1: Install symbiflow
|
||||
=========================
|
||||
-------------------------
|
||||
|
||||
To do that, a (custom) version of [symbiflow-magic](https://github.com/merledu/symbiflow-magic) is bundled with FemtoRV.
|
||||
Symbiflow-magic is a makefile that downloads and configures a pre-compiled version of symbiflow for ARTIX-7.
|
||||
@@ -15,7 +23,7 @@ $ make -f TOOLS/get_symbifow.mk
|
||||
It will download and install several packages (takes a while...)
|
||||
|
||||
Step 2: post-install step
|
||||
=========================
|
||||
-------------------------
|
||||
|
||||
Add anaconda initialization to your shell startup file as follows:
|
||||
```
|
||||
@@ -30,10 +38,86 @@ conda activate xc7
|
||||
|
||||
Start a new terminal window. If everything went well, the prompt should start with `(xc7)`.
|
||||
|
||||
Notes
|
||||
=====
|
||||
Yosys/NextPNR/ProjectXRay
|
||||
=========================
|
||||
|
||||
I'm currently working on another procedure that compiles
|
||||
Yosys/NextPNR/ProjectXRay directly from the up-to-date sources, because:
|
||||
- This version of symbiflow does not seem to support DSPs
|
||||
- Symbiflow includes a place-and-route tool that is not as efficient as nextPNR
|
||||
Step 1: yosys
|
||||
-------------
|
||||
|
||||
Follow setup instructions from [yosys website](https://github.com/YosysHQ/yosys)
|
||||
|
||||
*TL;DR*
|
||||
|
||||
Install prerequisites:
|
||||
```
|
||||
$ sudo apt-get install build-essential clang bison flex \
|
||||
libreadline-dev gawk tcl-dev libffi-dev git \
|
||||
graphviz xdot pkg-config python3 libboost-system-dev \
|
||||
libboost-python-dev libboost-filesystem-dev zlib1g-dev
|
||||
```
|
||||
Get the sources:
|
||||
```
|
||||
$ git clone https://github.com/YosysHQ/yosys.git
|
||||
```
|
||||
Compile and install it:
|
||||
```
|
||||
$ cd yosys
|
||||
$ make
|
||||
$ sudo make install
|
||||
```
|
||||
|
||||
Step 2: prjxray
|
||||
---------------
|
||||
|
||||
Either generate the database (but you need Vivado) or use a
|
||||
pre-generated one. OK, let's use the pre-generated one.
|
||||
|
||||
Follow the README from [prjwray](https://github.com/SymbiFlow/prjxray).
|
||||
|
||||
*TL;DR*
|
||||
|
||||
```
|
||||
$ git clone https://github.com/SymbiFlow/prjxray.git
|
||||
$ cd prjxray
|
||||
$ git submodule update --init --recursive
|
||||
$ make build
|
||||
$ sudo make install
|
||||
$ ./download-latest-db.sh
|
||||
$ sudo mkdir -p /usr/share/nextpnr/
|
||||
$ sudo cp -r database /usr/share/nextpnr/prjxray-db
|
||||
$ sudo apt-get install python3 python3-pip python3-yaml
|
||||
# NOT NEEDED ? $ sudo -H pip3 install -r requirements.txt # Rem: Arch Linux and Fedora uses *need* to read the README before.
|
||||
```
|
||||
|
||||
Step 3: nextpnr-xilinx
|
||||
======================
|
||||
Did not manage to build it with the gui, because on my box it gives a missing symbol error in boost-python, so I deactivated it.
|
||||
```
|
||||
$ git clone https://github.com/gatecat/nextpnr-xilinx.git
|
||||
$ cd nextpnr-xilinx
|
||||
$ git submodule init
|
||||
$ git submodule update
|
||||
$ mkdir build
|
||||
$ cd build
|
||||
$ cmake ../ -DARCH=xilinx -DBUILD_GUI=OFF -DBUILD_PYTHON=OFF
|
||||
$ make
|
||||
$ sudo make install
|
||||
```
|
||||
|
||||
One more thing, you will need to generate the chipdb (whatever that
|
||||
means, I do not understand everything here...). Learnt that from the 'building the Arty example' of
|
||||
[this webpage](https://github.com/gatecat/nextpnr-xilinx)). Needs to
|
||||
be adapted if you have a 100t instead of 35t.
|
||||
```
|
||||
$ cd nextpnr-xilinx
|
||||
$ python3 xilinx/python/bbaexport.py --device xc7a35tcsg324-1 --bba xilinx/xc7a35t.bba
|
||||
$ build/bbasm --l xilinx/xc7a35t.bba xilinx/xc7a35t.bin
|
||||
$ sudo mkdir -p /usr/share/nextpnr/xilinx-chipdb
|
||||
$ sudo cp xilinx/xc7a35t.bin /usr/share/nextpnr/xilinx-chipdb/
|
||||
```
|
||||
|
||||
Here we go ! Now time to
|
||||
- install openFPGALoader (see [the general toolchain tutorial](toolchain.md))
|
||||
- plug your ARTY
|
||||
- run `makeit.sh` in `basic/ARTY/ARTY_blink`
|
||||
If everything went well, you will see a colorful blinky !
|
||||
|
||||
Reference in New Issue
Block a user