124 lines
5.9 KiB
Markdown
124 lines
5.9 KiB
Markdown
FEMTORV32 / FEMTOSOC: a minimalistic RISC-V CPU
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===============================================
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_(Everything can fit on the IceStick < 1280 LUTs)_
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Quick links:
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- [IceStick tutorial](TUTORIALS/IceStick.md)
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- [IceBreaker tutorial](TUTORIALS/IceBreaker.md)
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- [ULX3S tutorial](TUTORIALS/ULX3S.md)
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- [ECP5 eval board tutorial](TUTORIALS/ECP5_EVN.md)
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- [FOMU tutorial](TUTORIALS/FOMU.md)
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- [ARTY tutorial](TUTORIALS/arty.md)
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- [LiteX tutorial](https://github.com/BrunoLevy/learn-fpga/tree/master/LiteX)
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- [Ice4Pi tutorial](TUTORIALS/Ice4Pi.md)
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- [Adding a new board](TUTORIALS/newboard.md)
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- [More documentation...](TUTORIALS/README.md)
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External links:
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- [A tutorial on YouTube by Shawn Hymel](https://www.youtube.com/watch?v=gJno9TloDj8)
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- [A tutorial on YouTube (episode 2)](https://t.co/MG9aPi1l3h)
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Features
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--------
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- Comes in different variants: quark (RV32I), electron (RV32IM),
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intermissum (RV32IM + irq), gracilis (RV32IMC + irq),
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petitbateau (RV32IMFC + irq).
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- Synthesis using the freeware tools (Yosys and nextpnr).
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- Main goal: to be used for teaching, easy to read, fitting on the ICEstick,
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fun demos (graphics), equip students for approx. $40.
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- Disclaimer: I'm no FPGA expert, please feel free to comment, to
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give me some advice !
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- Runs at 80MHz on the ICEStick and on the ULX3S.
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- 6kb RAM (ICEStick) or 256kb (ULX3S)
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- Firmware can be generated with gnu RISC-V toolsuite (script included), in C or in assembly.
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- SOC memory-mapped device drivers and hardware for UART, built-in LEDs, OLed display, led matrix.
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- femtolibC, femtoGL (everything fits in 6kb).
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- includes @ultraembedded's fat_io_lib (access to FAT filesystem on SDCards).
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- "femtOS" virtual output support: redirects printf() to UART, OLED screen (or led matrix, WIP).
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- many RISC-V assembly and C demo programs, including graphics for the OLED display.
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- now directly available in [LiteX](https://github.com/enjoy-digital/litex),
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see [tutorial](https://github.com/BrunoLevy/learn-fpga/blob/master/FemtoRV/TUTORIALS/litex.md)
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LUT count (FemtoRV32 + FemtoSOC)
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--------------------------------
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Statistics measured with ICE40/IceStick target.
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| Parameter | value1 | value2 | value3 |
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|----------------------|--------|--------|--------|
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| NRV_TWO_STAGE_SHIFTER| ON | OFF | OFF |
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| NRV_NEGATIVE_RESET | OFF | OFF | OFF |
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| NRV_IO_LEDS | ON | ON | ON |
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| NRV_IO_UART | ON | ON | OFF |
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| NRV_IO_SSD1351 | OFF | OFF | OFF |
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| NRV_IO_MAX7219 | OFF | OFF | OFF |
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| NRV_IO_SPI_FLASH | OFF | OFF | OFF |
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| NRV_FREQ | 50 | 50 | 50 |
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| NRV_RAM | 6144 | 6144 | 1024 |
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| NRV_COUNTERS | OFF | OFF | OFF |
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| NRV_COUNTERS_64 | OFF | OFF | OFF |
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| NRV_RV32M | OFF | OFF | OFF |
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| | | | |
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| LUT count | 1180 | 1140 | 980 |
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First column is a standard configuration for IceStick (UART and LED configured, 6Kb RAM, two-level shifter). This
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corresponds to the second line of the Dhrystones test. Second column measures the impact of the two-level shifter
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(eats up 40 LUTs). Third column is a minimalistic configuration, with no peripheral (just LEDs) and minimal RAM,
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to have an idea of how many LUTs the processor alone uses (less than 1000, achievement unlocked !).
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FemtoRV32 makes a compromise between complexity (the sources fit in 1000 lines of Verilog and - I think - are easy to read),
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LUT count (1000 is also the magic number here) and performance (around 1000 Dhrystones/s/MHz, most instructions take between
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2 and 3 cycles).
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FemtoRV32 License
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-----------------
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FemtoRV is licensed under the *Three-clause BSD* license:
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```
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Copyright (c) 2020-2021, Bruno Levy
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are
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met:
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* Redistributions of source code must retain the above copyright
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notice, this list of conditions and the following disclaimer.
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* Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in the
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documentation and/or other materials provided with the distribution.
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* Neither the name of the <copyright holder> nor the names of its
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contributors may be used to endorse or promote products derived from
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this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT
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HOLDER> BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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```
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References to other RISC-V cores
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--------------------------------
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- The reference: Claire Wolf's [picorv32](https://github.com/cliffordwolf/picorv32) (borrowed many ideas from there).
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- The smallest RISC-V: [SERV](https://github.com/olofk/serv), you can fit 5 instances (!) in 1000 LUTs.
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- Faster cores, Linux capable cores: [biriscv](https://github.com/ultraembedded/biriscv/), [VexRiscv](https://github.com/SpinalHDL/VexRiscv)
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- FemtoRV32's best friend: [ICE-V](https://github.com/sylefeb/Silice/tree/master/projects/ice-v),
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written in [Silice](https://github.com/sylefeb/Silice/) (a higher-level HDL)
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- DarkRiscv
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- Domipheus RPU
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- LamndaConcept Minerva
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- Glacial
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- neorv32
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- j-core
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- Syntacore scr1
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