23 lines
497 B
Verilog
23 lines
497 B
Verilog
`ifndef _add16_v
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`define _add16_v
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`include "halfadder.v"
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`include "fulladder.v"
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module Add16 (input [15:0] a, input [15:0] b, output [15:0] out);
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wire [16:1] c;
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genvar i;
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generate
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for (i=0; i<16; i=i+1)
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begin
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if (i==0)
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HalfAdder u1 (.a(a[i]), .b(b[i]), .sum(out[i]), .carry(c[i+1]));
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else
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FullAdder u1 (.a(a[i]), .b(b[i]), .c(c[i]), .sum(out[i]), .carry(c[i+1]));
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end
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endgenerate
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endmodule
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`endif
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