20 lines
289 B
Verilog
20 lines
289 B
Verilog
`include "add16.v"
|
|
|
|
module Add16_test;
|
|
reg [15:0] a, b;
|
|
wire [15:0] out;
|
|
|
|
integer i;
|
|
|
|
initial begin
|
|
$dumpfile("add16_tb.vcd");
|
|
$dumpvars;
|
|
a=123;
|
|
b=456;
|
|
#1;
|
|
$finish();
|
|
end
|
|
|
|
Add16 u1(.a(a), .b(b), .out(out));
|
|
endmodule
|