50 lines
1.2 KiB
Verilog
50 lines
1.2 KiB
Verilog
`ifndef _alu_v
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`define _alu_v
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`include "not16.v"
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`include "mux4way16.v"
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`include "add16.v"
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`include "and16.v"
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`include "or8way.v"
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`include "nor.v"
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module ALU (input [15:0] x,
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input [15:0] y,
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input zx,
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input nx,
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input zy,
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input ny,
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input f,
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input no,
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output [15:0] out,
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output zr,
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output ng);
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wire [15:0] x_inv, x_arg;
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wire [15:0] y_inv, y_arg;
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wire [15:0] sum, prod;
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wire [15:0] sum_inv, prod_inv;
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wire zr0, zr1;
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Not16 u1 (.in(x), .out(x_inv));
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Mux4Way16 u2 (.a(x), .b(x_inv), .c(16'h0000), .d(16'hFFFF), .sel({zx, nx}), .out(x_arg));
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Not16 u3 (.in(y), .out(y_inv));
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Mux4Way16 u4 (.a(y), .b(y_inv), .c(16'h0000), .d(16'hFFFF), .sel({zy, ny}), .out(y_arg));
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Add16 u5 (.a(x_arg), .b(y_arg), .out(sum));
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And16 u6 (.a(x_arg), .b(y_arg), .out(prod));
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Not16 u7 (.in(sum), .out(sum_inv));
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Not16 u8 (.in(prod), .out(prod_inv));
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Mux4Way16 u9 (.a(prod), .b(sum), .c(prod_inv), .d(sum_inv), .sel({no, f}), .out(out));
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Or8Way u10 (.in(out[15:8]), .out(zr0));
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Or8Way u11 (.in(out[7:0]), .out(zr1));
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Nor u12 (.a(zr0), .b(zr1), .out(zr));
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assign ng=out[15];
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endmodule
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`endif
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