77 lines
1.9 KiB
Verilog
77 lines
1.9 KiB
Verilog
`include "alu.v"
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module ALU_test;
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reg [15:0] x, y;
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reg zx, nx, zy, ny, f, no;
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wire [15:0] out;
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wire zr, ng;
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integer i;
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initial begin
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$dumpfile("alu_tb.vcd");
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$dumpvars;
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x=16'hAA55;
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y=16'h5555;
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{zx, nx, zy, ny, f, no}=6'b101010; // 0
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#1; // should get 0
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{zx, nx, zy, ny, f, no}=6'b111111; // 1
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#1; // should get 1
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{zx, nx, zy, ny, f, no}=6'b111010; // -1
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#1; // should get -1
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{zx, nx, zy, ny, f, no}=6'b001100; // x
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#1; // should return 0xAA55
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{zx, nx, zy, ny, f, no}=6'b110000; // y
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#1; // should return 0x5555
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{zx, nx, zy, ny, f, no}=6'b001101; // !x
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#1; // should return 0x55AA
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{zx, nx, zy, ny, f, no}=6'b110001; // !y
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#1; // should return 0xAAAA
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{zx, nx, zy, ny, f, no}=6'b001111; // -x
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#1; // should return 0x55AB
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{zx, nx, zy, ny, f, no}=6'b110011; // -y
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#1; // should return 0xAAAB
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{zx, nx, zy, ny, f, no}=6'b011111; // x++
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#1; // should return 0xAA56
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{zx, nx, zy, ny, f, no}=6'b110111; // y++
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#1; // should return 0x5556
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{zx, nx, zy, ny, f, no}=6'b001110; // x--
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#1; // should return 0xAA54
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{zx, nx, zy, ny, f, no}=6'b110010; // y--
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#1; // should return 0x5554
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{zx, nx, zy, ny, f, no}=6'b000010; // x+y
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#1; // should return 0xFFAA
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{zx, nx, zy, ny, f, no}=6'b010011; // x-y
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#1; // should return 0x5500
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{zx, nx, zy, ny, f, no}=6'b000111; // y-x
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#1; // should return 0xAB00
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{zx, nx, zy, ny, f, no}=6'b000000; // x&y
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#1; // should return 0x0055
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{zx, nx, zy, ny, f, no}=6'b010101; // x|y
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#1; // should return 0xFF55
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$finish();
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end
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ALU u1(.x(x), .y(y), .zx(zx), .nx(nx), .zy(zy), .ny(ny), .f(f), .no(no), .out(out), .zr(zr), .ng(ng));
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endmodule
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