15 lines
226 B
Verilog
15 lines
226 B
Verilog
`ifndef _and_v
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`define _and_v
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`include "nand.v"
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`include "not.v"
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module And (input a, input b, output out);
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wire out_bar;
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Nand u1(.a(a), .b(b), .out(out_bar));
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Not u2(.in(out_bar), .out(out));
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endmodule
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`endif
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