20 lines
376 B
Verilog
20 lines
376 B
Verilog
`ifndef _mux_v
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`define _mux_v
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`include "not.v"
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`include "and.v"
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`include "or.v"
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module Mux (input a, input b, input sel, output out);
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wire sel_bar;
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wire a_sel;
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wire b_sel;
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Not u1 (.in(sel), .out(sel_bar));
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And u2 (.a(a), .b(sel_bar), .out(a_sel));
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And u3 (.a(b), .b(sel), .out(b_sel));
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Or u4 (.a(a_sel), .b(b_sel), .out(out));
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endmodule
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`endif
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